SADP Patterning Method Using Cover Layer Planarization

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Solution Overview

Problem

The self-aligned double patterning (SADP) approach in semiconductor manufacturing faces issues such as etching recess loading on hard mask layers and spacer shape irregularities, which affect manufacturing yield and device performance.

Innovation Solution

A patterning method involving a cover layer applied over hard mask layers, spacers, and mask patterns, followed by a planarization process to remove the cover layer and mask patterns, preventing etching recesses and ensuring uniformity of the top surfaces, thereby enhancing pattern transfer performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the SADP approach is used to achieve smaller critical dimensions, then the patterning capability is improved, but etching recesses are formed on the hard mask layer and spacer shape irregularities occur

Engineering Contradiction:
Improvepatterning precisionVSAvoidmanufacturing yield
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A planarization layer is introduced as an intermediary between the spacer and the etching process. This layer acts as a mediator that prevents direct contact between the etchant and the hard mask layer, thereby eliminating etching recesses while preserving the spacer pattern integrity and improving manufacturing yield

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The planarization layer is formed in advance before the spacer pattern transfer etching process. This preliminary action creates a protective barrier that prevents etching recesses from forming on the hard mask layer during subsequent etching operations, ensuring both patterning precision and manufacturing yield

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the SADP approach is used to achieve smaller critical dimensions, then the patterning capability is improved, but spacer shape irregularities occur

Engineering Contradiction:
Improvepatterning precisionVSAvoidspacer shape uniformity
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The planarization layer serves as a protective intermediary that shields the spacer sidewalls during etching operations. This intermediary layer prevents direct etchant attack on the spacer, maintaining uniform spacer shapes and eliminating shape irregularities while preserving the achieved patterning precision

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The planarization layer is formed beforehand to provide cushioning protection to the spacer structure. This prior cushioning prevents etching-induced shape irregularities by absorbing the harmful effects of the etching process, ensuring uniform spacer shapes throughout manufacturing

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS10475649B2Patterning method
Publication Date: 2019.11.12 UNITED MICROELECTRONICS CORP
  • US10475649B2 patent drawing
  • US10475649B2 patent drawing
  • US10475649B2 patent drawing

AI summary

A patterning method includes the following steps. A hard mask layer is formed on a substrate. Mandrels are formed on the hard mask layer. Mask patterns are formed on the mandrels. Each of the mask patterns is formed on one of the mandrels. Spacers are formed on the hard mask layer. Each of the spacers is formed on a sidewall of one of the mandrels and on a sidewall of one of the mask patterns. A cover layer covering the hard mask layer, the spacers and the mask patterns is formed. A planarization process is performed to remove the cover layer on the mask patterns and the spacer and remove the mask patterns. A part of the cover layer remains between the spacers after the planarization process. The mandrels and the cover layer are removed after the planarization process.