SADP Dense Line Patterning for 3D Memory Alignment Tolerance
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Solution Overview
Problem
As feature sizes of planar memory cells approach their lower limit, traditional planar fabrication techniques become challenging and costly, limiting memory density.
Innovation Solution
A method for forming dense line patterns using self-aligned double patterning (SADP) for three-dimensional (3D) memory, involving the exposure and removal of mandrel lines, formation of dielectric spacers, and deposition of conductive layers to create conductive lines between spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional planar fabrication techniques are used to scale memory cells to smaller sizes, then manufacturing process becomes simpler, but memory density approaches an upper limit and feature sizes approach lower limit
Solution Approach 1:
The patent applies segmentation by dividing the single patterning process into multiple stages: first forming mandrel lines, then forming spacers around them, and finally removing mandrels to create the final pattern. This multi-stage approach enables fabrication of features at 10nm and below, overcoming the resolution limits of traditional single-step lithography while managing process complexity through systematic breakdown of steps.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer formation. By depositing conformal dielectric layers around mandrel lines and then anisotropically etching to form vertical spacers, the process exploits the third dimension (vertical height) to create horizontal patterns that are smaller than the lithography resolution limit, thereby achieving higher precision without proportionally increasing planar process complexity.
2Manufacturing precision
If feature sizes are reduced to increase memory density, then memory density improves, but alignment tolerance decreases and manufacturing becomes more challenging
Solution Approach 1:
The spacer formation process is self-aligned: the dielectric spacers automatically form conformally around the mandrel lines, and the subsequent anisotropic etching creates spacers that are precisely positioned relative to the original mandrel centers. This self-aligned mechanism inherently provides alignment tolerance, as the spacer width is determined by the conformal deposition thickness rather than by alignment between separate lithography steps, thereby maintaining reliability at reduced feature sizes.
3Ease of manufacture
If self-aligned double patterning is used to form dense line patterns, then alignment tolerance improves and manufacturing complexity reduces, but process steps increase
Solution Approach 1:
The patent merges the patterning and spacing functions into a unified self-aligned process. The conformal dielectric deposition simultaneously serves as both the spacer material layer and the alignment reference, while the anisotropic etching step combines pattern transfer and spacer formation in one operation. This merging reduces the need for separate alignment steps between lithography and etching, thereby easing manufacturing despite the additional deposition and etching steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of dense line patterns with improved alignment tolerance and reduced manufacturing complexity, enhancing memory density and reducing costs in 3D memory architectures.
Implementation Method 1
disposing a dielectric layer over the mandrel lines of the page buffer
Implementation Method 2
disposing a dielectric layer over the mandrel lines of the page buffer
Implementation Method 3
disposing a conductive layer and forming conductive lines in between the dielectric spacers
Implementation Method 4
disposing a conductive layer and forming conductive lines in between the dielectric spacers
Data Source
AI summary
A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.