SADP Mask Structure for Uniform DRAM Capacitor Hole Etching
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Solution Overview
Problem
The asymmetrical topographies and depth differences in traditional Self-Aligned Double Patterning (SADP) mask patterns lead to inconsistent capacitor hole formation in DRAM, affecting storage capacity and stability, especially as DRAM size decreases.
Innovation Solution
A method involving the sequential stacking of a pattern transfer layer, etching stop layer, sacrificial layer, and hard mask layer, followed by patterning and removal steps to form mask patterns with asymmetrical topographies, which are then used to etch a to-be-etched material layer, resulting in uniform capacitor holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Self-Aligned Double Patterning (SADP) is used to define capacitor hole patterns, then pattern density is improved, but asymmetrical topographies and depth differences cause etching inconsistency and dislocation
Solution Approach 1:
The patent intentionally introduces asymmetrical dummy patterns (first and second dummy patterns) with different heights on opposite sides of the capacitor hole pattern. These dummy patterns compensate for the asymmetrical topographies inherent in SADP, creating symmetrical effective etching conditions and eliminating depth differences that cause etching inconsistency and dislocation.
2Adaptability or versatility
If material layers with different selection ratios are used in SADP, then patterning flexibility is improved, but load effects cause depth differences on mask pattern sides
Solution Approach 1:
The patent applies counterweight by introducing dummy patterns with compensatory heights that offset the depth differences caused by load effects. The first dummy pattern with height H1 compensates for the deeper side, while the second dummy pattern with height H2 compensates for the shallower side, balancing the overall mask pattern depth and eliminating etching inconsistencies.
3Productivity
If DRAM size is reduced to increase storage capacity, then storage density is improved, but asymmetrical mask patterns cause further etching dislocation and inconsistency
Solution Approach 1:
The patent introduces asymmetrical dummy patterns with specific height differences designed to compensate for the asymmetrical topographies that become more pronounced at smaller DRAM dimensions. This ensures consistent etching performance and alignment accuracy even as device size decreases and storage density increases.
Data Source
AI summary
A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.