SADP Memory Trench Patterning for Alignment and Leakage Control
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Solution Overview
Problem
Advanced semiconductor technology nodes face challenges in increasing memory device density due to misalignment and leakage issues, which are exacerbated by the narrowing process window and difficulty in reducing minimum feature size during lithography-based manufacturing.
Innovation Solution
A method of manufacturing memory devices using a self-aligned double patterning (SADP) process that involves forming a semiconductor substrate with an active area, creating a series of hard masks and spacers to define the active area without the need for multiple photomasks, thereby reducing misalignment and improving precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photomasks are used in lithography to define the active area, then the active area can be defined with multiple patterns, but misalignment and leakage issues arise due to the narrowing process window
Solution Approach 1:
The spacer structure forms automatically around the core through conformal deposition, self-defining the pattern positions without requiring additional photomasks. The spacer's outer surface directly defines the active area boundary, eliminating the need for manual alignment between multiple lithography steps.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structures by forming spacers that extend around the core. This vertical dimension provides an additional degree of freedom for defining patterns, allowing precise lateral positioning through vertical conformal deposition.
2Productivity
If the minimum feature size is reduced to increase device density, then more memory cells can be packed, but misalignment and leakage among memory cells increase
Solution Approach 1:
The spacer automatically forms with precise dimensional control through conformal deposition thickness, self-defining the trench pattern positions and spacing. This self-aligned mechanism maintains high alignment precision even when the lateral dimensions are reduced to increase device density.
Solution Approach 2:
The patent controls the spacer thickness through precise deposition parameters, which directly determines the lateral spacing between trenches. By adjusting the deposition thickness parameter, the minimum feature size can be reduced while maintaining consistent alignment precision across the structure.
3Ease of manufacture
If conventional lithography patterning is used, then the manufacturing process is straightforward, but the process window narrows and limits reduction of minimum feature size
Solution Approach 1:
The spacer structure self-defines the final pattern through conformal deposition and selective removal, eliminating the need for complex multi-step lithography alignment procedures. This self-aligned approach simplifies the manufacturing process while enabling precise feature size control that is not limited by conventional lithography resolution.
Data Source
AI summary
The present application provides a memory device and a method of manufacturing the memory device. The method includes steps of providing a semiconductor substrate defined with an active area disposed over or in the semiconductor substrate; forming a first hard mask over the semiconductor substrate; forming a core over the first hard mask, wherein the core has a strip portion and a protruding portion protruding laterally from the strip portion; forming a spacer surrounding the core; removing the strip portion of the core; removing portions of the first hard mask exposed through the spacer and the protruding portion of the core; forming a second hard mask surrounding the first hard mask; removing the first hard mask; and removing portions of the semiconductor substrate exposed through the second hard mask to form a trench surrounding the active area.