Self-Aligned Double Patterning for Semiconductor Circuit Density
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Solution Overview
Problem
Conventional double patterning technology in semiconductor manufacturing faces challenges in forming uniform circuit profiles at nanometer scales, leading to micro-loading effects and requiring additional dummy patterns that occupy valuable layout space, hindering increased circuit density.
Innovation Solution
A positive self-aligned double patterning (P-SADP) process that forms line features with uniform profiles by sequentially forming a target layer, hard mask layer, and core bodies on a substrate, using spacers to pattern the hard mask layer, and removing core bodies outside predetermined regions to create equally spaced hard mask bodies, eliminating the need for dummy patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional double patterning technology is used to form circuit patterns at nanometer scales, then circuit density can be improved, but micro-loading effects cause non-uniform circuit profiles and poor critical dimension uniformity
Solution Approach 1:
The patent segments the patterning process into multiple distinct steps: forming mandrels at a first pitch, depositing spacers, selectively removing mandrels, and forming final patterns at a second pitch. This segmentation allows each step to be optimized independently, achieving both high density and uniform profiles by controlling the formation of mandrels and spacers separately rather than attempting to form all features in a single exposure step.
Solution Approach 2:
The patent performs preliminary actions by first forming mandrels with uniform profiles before using them as templates for the final pattern. The mandrels are formed with controlled dimensions and uniformity, then spacers are deposited on them. This preliminary structuring ensures that the final pattern inherits the uniformity of the mandrels while achieving the desired high density through the spacer formation process.
2Manufacturing precision
If dummy patterns are added to compensate for micro-loading effects, then circuit profile uniformity can be improved, but layout space is consumed reducing overall circuit density
Solution Approach 1:
The patent employs self-aligned spacer formation where the spacers are automatically positioned relative to the mandrels through conformal deposition. This self-alignment mechanism inherently compensates for density variations without requiring external dummy patterns. The spacer width is controlled by deposition thickness rather than lithographic exposure, making the process self-regulating and eliminating the need for space-consuming dummy features to maintain uniformity.
3Manufacturing precision
If photolithographic exposure is used to form fine patterns, then circuit features can be created, but physical limitations prevent achieving half-pitch below 45 nm
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional spacer formation. Instead of attempting to directly expose sub-45nm features through photolithography, the method uses vertical spacer deposition on mandrels to define the final pattern dimensions. The critical dimension is controlled by thin film deposition thickness rather than optical resolution, effectively moving the patterning constraint from the optical domain to the thin film deposition domain where sub-45nm precision is achievable.
Data Source
AI summary
A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer.