Semiconductor Pattern Transfer Layout for SADP Etch Load Mismatch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The self-aligned-doubled patterning (SADP) process in semiconductor manufacturing results in misalignment and structural defects due to differing etching load effects between storage and peripheral circuit regions, affecting the accuracy of pattern formation.
Innovation Solution
A patterning method involving the formation of first and second hard masks, with a buffer layer to cover and correct structural defects in second hard masks, allowing for accurate patterning of the barrier and pattern transfer layers, ensuring precise feature transfer and reducing etching load effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned-doubled patterning (SADP) process is used to improve device integration, then manufacturing precision is improved, but structural defects occur in storage regions near peripheral circuit regions due to different etching load effects
Solution Approach 1:
The patent applies local quality by introducing a buffer layer specifically in the storage region near the peripheral circuit region, while other regions proceed with the standard SADP process. This localized modification compensates for the etching load effect differences between storage and peripheral circuit regions, preventing structural defects in the affected area without altering the overall patterning process.
Solution Approach 2:
The buffer layer is formed before the final patterning step, preliminarily compensating for the etching load effect differences between storage and peripheral circuit regions. This preliminary action ensures that when the etching process occurs, the buffer layer already provides the necessary compensation to prevent structural defects.
2Productivity
If different etching load effects are accepted between storage and peripheral circuit regions, then device integration is improved, but misalignment of key dimensions occurs after patterning
Solution Approach 1:
The patent introduces a buffer layer specifically in the storage region adjacent to the peripheral circuit region to locally compensate for etching load effects. This localized modification ensures that key dimensions in the affected area align correctly with peripheral circuit regions, while maintaining high device integration through the SADP process in other areas.
3Manufacturing precision
If buffer layer is added to compensate for etching load effects, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The buffer layer is introduced only in the specific storage region near the peripheral circuit region where etching load effects cause problems, rather than applying it uniformly across the entire device. This localized approach improves manufacturing precision in the critical area while minimizing the increase in overall process complexity.
Data Source
AI summary
Embodiments of the present disclosure provide a patterning method and a semiconductor structure. The method includes: providing a substrate, wherein the substrate includes adjacent storage regions and peripheral circuit regions; forming, on the substrate, a pattern transfer layer, the pattern transfer layer having a plurality of first hard masks, wherein the first hard masks extend along a first direction and are spaced apart from each other; forming a barrier layer on the pattern transfer layer; forming, on the barrier layer, a plurality of second hard masks, the plurality of second hard masks extending along a second direction, wherein the second hard masks are spaced apart from each other, and the second hard masks are located in the storage regions and second hard masks close to the peripheral circuit regions have structural defects.