SAGE Gate Endcap Architecture for Dense Gate-All-Around Layouts
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in scaling down transistor dimensions due to limitations in lithographic patterning, leading to increased gate capacitance and energy consumption, particularly in achieving tight diffusion end-to-end spacing without compromising mask registration accuracy.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures with gate-all-around devices, where a disposable spacer on semiconductor fin sidewalls determines gate endcap and contact overlap dimensions, allowing for self-aligned gate and trench contact endcaps without the need for extra length to account for mask mis-registration, and enabling more aggressive diffusion spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning is used to pattern transistor features, then mask registration accuracy can be maintained, but diffusion end-to-end spacing cannot be reduced sufficiently, leading to increased gate capacitance and energy consumption
Solution Approach 1:
The gate endcap isolation structure is formed preliminarily before the gate electrode is deposited. This preliminary formation of the isolation structure defines the exact position where the gate electrode should terminate, eliminating the need for additional endcap length to compensate for potential mask mis-registration during subsequent lithographic steps.
Solution Approach 2:
The gate endcap isolation structure serves as an intermediary element between the diffusion region and the gate electrode. It physically defines the boundary and provides a reference structure that eliminates the need for extra endcap length, thereby reducing gate capacitance while maintaining manufacturing precision.
2Reliability
If extra endcap length is added to account for mask mis-registration, then manufacturing robustness is improved, but transistor layout density decreases and device-to-device variability increases
Solution Approach 1:
The gate endcap isolation structure is formed using a self-aligned process where the isolation structure itself defines the boundary for the gate electrode. This self-service approach eliminates the need for additional endcap length to compensate for mask mis-registration, thereby maintaining manufacturing robustness while improving layout density.
3Area of stationary object
If diffusion spacing is reduced to increase device density, then layout density improves, but mask registration accuracy becomes compromised
Solution Approach 1:
The gate endcap isolation structure is formed preliminarily to define the exact gate termination position before lithographic patterning of the gate electrode. This preliminary definition allows for reduced diffusion spacing while maintaining manufacturing precision, as the isolation structure serves as a physical reference that eliminates sensitivity to mask registration errors.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.