SAGE Gate Endcap Architecture for Mask-Alignment-Limited GAA Scaling
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Solution Overview
Problem
Conventional lithographic processes struggle to scale gate endcap and trench contact endcap regions in semiconductor devices, leading to increased gate capacitance and degraded performance due to mask registration errors and limited diffusion spacing.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, where gate and trench contact endcaps are self-aligned to the starting semiconductor fin, eliminating the need for extra length to account for mask mis-registration and allowing for more aggressive diffusion spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern gate endcap and trench contact endcap regions, then device dimensions can be scaled down, but mask registration errors increase and diffusion spacing becomes restricted
Solution Approach 1:
The gate endcap isolation structure is formed in advance before the gate electrode pattern is transferred, creating a self-aligned reference that eliminates mask registration errors during subsequent lithography steps. This preliminary formation of the isolation structure at the fin level ensures precise alignment without requiring additional mask alignment precision.
Solution Approach 2:
The gate endcap isolation structure serves as an intermediary element that mediates between the fin structure and the gate electrode. It provides a physical reference that transfers alignment information from the fin level to the gate level, eliminating the need for precise mask registration between different lithography steps.
2Manufacturing precision
If conventional lithographic processes are used with extra length for mask mis-registration, then alignment tolerance is improved, but transistor layout density decreases
Solution Approach 1:
The gate endcap isolation structure is formed in advance before the gate electrode pattern is transferred, creating a self-aligned reference that eliminates mask registration errors during subsequent lithography steps. This preliminary formation of the isolation structure at the fin level ensures precise alignment without requiring additional mask alignment precision.
Solution Approach 2:
The gate endcap isolation structure is self-aligned to the fin structure through self-aligned etching processes, eliminating the need for external mask alignment. The structure serves itself as the alignment reference, removing the requirement for extra length to accommodate mask mis-registration errors.
3Length of moving object
If gate endcap regions are scaled down with conventional processes, then device size is reduced, but device-to-device variability increases
Solution Approach 1:
The gate endcap isolation structure is formed in advance before the gate electrode pattern is transferred, creating a self-aligned reference that eliminates mask registration errors during subsequent lithography steps. This preliminary formation of the isolation structure at the fin level ensures precise alignment without requiring additional mask alignment precision.
Solution Approach 2:
The gate endcap isolation structure serves as an intermediary element that mediates between the fin structure and the gate electrode. It provides a physical reference that transfers alignment information from the fin level to the gate level, eliminating the need for precise mask registration between different lithography steps.
Data Source
Figure 1(a)~1(b)
Figure 2
Figure 3(a)~3(b)
AI summary
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure comprising: a first channel region comprising first nanowires; a second channel region comprising second nanowires, the second channel region laterally spaced apart from the first channel region, and the first channel region having a width less than a width of the second channel region along a direction orthogonal to a source to drain direction; a first gate stack around the first nanowires; a second gate stack around the second nanowires; a first gate endcap wall laterally between and in contact with the first gate stack and the second gate stack, the first gate endcap wall having a top surface above a top surface of the first gate stack and above a top surface of the second gate stack; and a second gate endcap wall in contact with the second gate stack, the second gate endcap wall having a top surface above the top surface of the second gate stack, wherein the second gate stack is laterally between the second gate endcap wall and the first gate endcap wall.