Self-Aligned Gate Endcaps for Tighter Gate-All-Around Spacing
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors faces challenges in maintaining mobility improvement and short channel control as device dimensions approach the 10 nanometer node, with constraints on lithographic processes leading to trade-offs between critical dimension and spacing between features.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures with gate-all-around devices, which involve the fabrication of gate endcap isolation structures self-aligned to semiconductor fins and nanowires, allowing for tighter spacing and reduced lithographic dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional tri-gate fabrication processes are used on bulk silicon substrates, then manufacturing cost is reduced and fabrication complexity is lowered, but device density and layout area efficiency deteriorate due to larger required spacing between features
Solution Approach 1:
The patent implements self-aligned gate endcap structures that extend vertically from the gate electrode, creating a three-dimensional configuration. This vertical extension into the Z-dimension enables the gate to provide control over a larger area without increasing the planar footprint, thereby improving layout density while maintaining conventional fabrication processes.
Solution Approach 2:
The gate endcap structures are positioned within and aligned to the existing gate electrode structures, creating a nested configuration where the endcaps are contained within the lateral boundaries of the gates. This nesting approach allows additional functional structures to be added without requiring additional lateral spacing, thus improving density without increasing process complexity.
2Productivity
If feature dimensions are scaled down to increase device density, then the number of devices per chip area increases, but lithographic process constraints worsen due to the trade-off between critical dimension and spacing between features
Solution Approach 1:
The gate endcap structures are formed through a self-aligned process where the endcaps automatically position themselves relative to the gate electrodes without requiring additional lithographic patterning steps. The endcaps are created by depositing material conformally on the gate structures and then performing anisotropic etching, which self-aligns the endcaps to the gates based on the gate's physical presence, thereby eliminating lithographic spacing constraints.
Solution Approach 2:
The gate endcap structures are formed prior to final gate electrode patterning, allowing the endcaps to serve as pre-positioned alignment references for subsequent processing steps. This preliminary formation of the endcap structures enables tighter spacing between devices since the critical alignment is established before the most constrained lithographic steps are performed.
3Area of moving object
If tighter spacing between gate structures is implemented to improve layout density, then device capacity increases, but device-to-device variability in electrical parameters increases
Solution Approach 1:
The self-aligned formation of gate endcaps ensures that each endcap's position is determined by its associated gate electrode's physical location rather than by independent lithographic patterning. This self-alignment mechanism automatically compensates for variations in gate positioning, ensuring that endcaps are consistently positioned relative to their gates even when gates are tightly spaced, thereby reducing device-to-device variability in electrical parameters.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.