Self-Aligned Gate Endcap Contacts for Denser FinFET Layouts
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to constraints in lithographic processes, leading to trade-offs between feature dimension and spacing, and increased capacitance, which affects performance and density.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures with a perpendicular grid of insulating material allows for self-aligned gate and contact interconnects without requiring extra length for mask registration, reducing the need for lithographic patterning and improving transistor layout density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern multi-gate transistors, then mask registration accuracy can be maintained, but transistor layout area increases and density decreases
Solution Approach 1:
The patent merges the gate endcap formation with the contact alignment process by using the same lithographic mask for both features. This integration eliminates the need for separate mask registration steps, allowing reduced layout area while maintaining manufacturing precision through the combined patterning approach.
Solution Approach 2:
The patent transitions from planar layout to three-dimensional multi-gate structures with vertical fins. By utilizing the vertical dimension for the gate structure, the effective active area is increased without proportionally increasing the planar footprint, thereby improving density while maintaining mask registration accuracy through self-aligned processes.
2Manufacturing precision
If additional masks are used for gate endcap patterning, then lithographic control is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent combines the patterning of gate endcaps with the patterning of contacts using a single lithographic mask. This merging of functions reduces the total number of masks required while maintaining lithographic control through the integrated design that allows both features to be defined in the same patterning step.
Solution Approach 2:
The lithographic mask is designed to serve multiple functions simultaneously: defining gate endcaps, defining contacts, and providing alignment references for subsequent processing steps. This multi-functionality reduces device complexity by eliminating the need for dedicated masks for each feature while maintaining precise lithographic control.
3Area of stationary object
If transistor dimensions are reduced to increase density, then capacity increases, but capacitance between adjacent features increases affecting performance
Solution Approach 1:
The patent employs vertical fins extending from the substrate to form the gate structure. This three-dimensional configuration increases the effective channel area and transistor capacity without proportionally increasing the planar footprint. The vertical orientation also reduces parasitic capacitance between adjacent transistors by increasing vertical separation while maintaining horizontal packing density.
Solution Approach 2:
The gate structure is segmented into multiple vertical fins rather than a single planar gate. This segmentation increases the effective gate area for controlling the channel while distributing the capacitance load across multiple separated structures. The fins are spaced to minimize parasitic coupling while maximizing the total active area within the reduced footprint.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.