Self-Aligned Gate Endcap Isolation Without Fin End Gaps
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in scaling down multi-gate transistors due to constraints in lithographic processes, leading to trade-offs between feature size and spacing, which result in increased gate capacitance and energy consumption, and issues with fin end gaps causing electrical shorts and decreased yield.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures without fin end gaps, achieved through selective sidewall fin spacer deposition and angled helmet deposition, eliminates the need for extra endcap length for mask registration and reduces lithographic operations, allowing for tighter spacing and increased device yield by ensuring gate-to-contact alignment without fin end gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern semiconductor features, then feature size can be reduced, but spacing between features must be increased
Solution Approach 1:
The gate endcap isolation structure is formed preliminarily before the gate structure, using selective spacer deposition on fin sidewalls to pre-establish the exact position where the gate should end. This preliminary positioning action eliminates the need for additional mask registration margins, allowing features to be packed tighter without increasing spacing requirements.
Solution Approach 2:
The spacer structure serves itself as the alignment reference for subsequent gate patterning. Instead of requiring separate alignment marks and registration processes, the spacer automatically defines the gate endpoint position through its physical presence, making the system self-aligning and eliminating spacing penalties associated with conventional lithographic registration.
2Measurement precision
If extra endcap length is added for mask registration, then alignment accuracy is improved, but device density decreases
Solution Approach 1:
The spacer structure serves itself as the alignment reference for subsequent gate patterning. Instead of requiring separate alignment marks and registration processes, the spacer automatically defines the gate endpoint position through its physical presence, making the system self-aligning and eliminating spacing penalties associated with conventional lithographic registration.
Solution Approach 2:
The invention extracts the alignment function from the lithographic mask registration process and transfers it to the physical spacer structure. By removing the dependency on mask alignment and registration margins, the design eliminates the extra endcap length that would otherwise be required, thereby maintaining high device density while achieving precise alignment.
3Ease of manufacture
If fin end gaps are present in conventional architectures, then manufacturing is simpler, but electrical shorts occur and yield decreases
Solution Approach 1:
The gate endcap isolation structure acts as an intermediary element between the fin and the gate structure. This isolation structure, formed by selective spacer deposition, physically fills the gap that would otherwise exist at the fin end, preventing electrical shorts while maintaining the simplicity of the manufacturing process by using the same spacer deposition technique already employed for sidewall alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more aggressive scaling of diffusion spacing, reduces device variability, and decreases the cost per transistor by eliminating fin end gaps, thereby improving transistor layout density and performance.
Implementation Method 1
selective sidewall fin spacer deposition
Implementation Method 2
angled helmet deposition
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.