SAIF Generation for Circuit Design Emulation
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Solution Overview
Problem
Traditional methods for estimating power consumption in emulated circuit designs are time-intensive and require significant resources, often taking up to 8000 CPU hours for designs with 400 million logic gates, due to the need to extract and process large amounts of signal waveforms.
Innovation Solution
The method involves segregating the circuit design into subnets and inserting SAIF logic with counters to generate power consumption data within the emulator, using field programmable gate arrays (FPGAs) to efficiently calculate and consolidate SAIF files, reducing the need for extensive data transfer and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all sequential and combinational signals are dumped from the emulator, then complete SAIF data is obtained, but data transfer time increases due to bandwidth limits
Solution Approach 1:
The circuit design is divided into multiple subnets, and SAIF logic is inserted into each subnet independently. This segmentation allows parallel generation of SAIF data for different subnets, reducing the total time required to capture complete switching activity data without requiring to dump all signals simultaneously through bandwidth-limited interfaces.
2Measurement precision
If all sequential and combinational signals are dumped, then complete power consumption data is captured, but significant additional hardware resources are required inside the emulator
Solution Approach 1:
The SAIF logic including counters is extracted and inserted only at the output of each subnet rather than monitoring all internal signals. This extraction approach captures the essential switching activity data needed for power consumption calculation while minimizing the additional hardware resources required within the emulator, as only the net outputs need to be monitored.
3Device complexity
If only sequential elements are dumped and combinational signals are reconstructed offline, then hardware resources are reduced, but the reconstruction process becomes slow
Solution Approach 1:
SAIF logic with counters is preliminarily inserted into each subnet during the emulation setup phase, so that switching activity data is captured and stored in SAIF format during the actual emulation run. This preliminary action eliminates the need for slow offline reconstruction of combinational signal activity, as the data is already captured in the required format during emulation, significantly improving productivity.
Data Source
AI summary
A method for calculating switching interface activity format (SAIF) for a circuit design includes segregating the circuit design into a plurality of hardware look up tables (LUTs), inserting switching interface activity format (SAIF) counter logic, and inserting a multiplexer between the LUTs and the SAIF counter logic. The SAIF counter logic includes shadow logic, at least one counter, and memory. The method further includes (i) selecting a previously-unselected LUT by switching the multiplexer to the selected LUT, (ii) executing a test through the selected LUT and the SAIF counter logic to generate SAIF data for the LUT, (iii) storing the SAIF data for the selected LUT in the memory, and (iv) continuing with (i) through (iii) until each of the plurality of LUTs is selected. The method further involves merging the SAIF data from each selected LUT into a consolidated SAIF file with SAIF data for the circuit design.