Salicide Capping Layer for FinFET Source/Drain Protection

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in manufacturing complex and scaled-down semiconductor devices, such as FinFETs, which require advanced processing techniques to form efficient salicide layers that maintain the integrity and functionality of source/drain structures while allowing for increased surface area for electrical connections.

Innovation Solution

A semiconductor device structure is developed with a salicide layer formed over the source/drain structure, where the salicide layer extends to cover more area for better electrical connectivity, and a capping layer is used to protect the salicide layer, preventing damage to the source/drain structure during processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the salicide layer is formed to cover more area for better electrical connectivity, then the electrical conductivity is improved, but the source/drain structure may be damaged during processing

Engineering Contradiction:

Improveelectrical connectivityVSAvoiddamage to source/drain structure

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A capping layer is introduced as an intermediary between the salicide layer and the source/drain structure. This capping layer protects the source/drain structure from damage during salicide formation while allowing the salicide layer to extend over the source/drain structure to improve electrical connectivity. The capping layer serves as a protective mediator that enables the beneficial extension of the salicide layer without causing harm to the underlying structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The capping layer is formed before the salicide layer deposition. This preliminary action of placing the protective capping layer in advance prevents damage to the source/drain structure during subsequent salicide formation processes. By performing the protective action beforehand, the source/drain structure is shielded from potential harm while still allowing the salicide layer to be formed over it for improved electrical connectivity.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the geometric size is scaled down to increase functional density, then production efficiency is improved, but the manufacturing complexity increases

Engineering Contradiction:

Improveproduction efficiencyVSAvoidmanufacturing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The structure is segmented into multiple distinct layers: the source/drain structure, the capping layer, and the salicide layer. This segmentation allows each layer to be formed and optimized independently, simplifying the manufacturing process despite the scaled-down dimensions. By dividing the structure into functional segments, the patent enables precise control over each layer's formation while maintaining overall device complexity management.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The capping layer provides localized protection specifically where needed - over the source/drain structure during salicide formation. This local quality approach allows the protective function to be applied precisely where required without affecting other areas of the device. The capping layer's selective placement enables improved electrical connectivity through extended salicide coverage while maintaining manufacturing simplicity through targeted rather than universal application.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the electrical connectivity and reduces resistance in the semiconductor device structure, improving its performance and preventing damage to the source/drain structure during salicide layer formation, thus suitable for various technology generations including 16 nm, 10 nm, and 7 nm nodes.

Implementation Method 1

a salicide layer formed over the source/drain structure

Methodology Applied

Scientific EffectChemical reaction: Chemical Bonding

Implementation Method 2

a capping layer is used to protect the salicide layer, preventing damage to the source/drain structure during processing

Methodology Applied

Scientific EffectPhysical barrier protection: Physical Containment

Data Source

PatentUS20220376079A1Semiconductor device structure

Publication Date: 2022.11.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.