Au-Free Salicide Source-Drain for III-V HEMT Uniformity
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Solution Overview
Problem
Conventional methods for forming high electron mobility transistors (HEMTs) using III-V semiconductor compounds face challenges in achieving uniform electrical performance and controlling etching uniformity across semiconductor chip regions, leading to inconsistent device characteristics and potential contamination issues due to the use of gold in source/drain features.
Innovation Solution
The method involves epitaxially growing a second III-V compound layer on a first III-V compound layer, partially etching to form through holes, forming salicide source/drain features by annealing silicon and metal layers, and creating a gate electrode structure, which improves electrical connection and eliminates gold contamination by using Au-free salicide source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form HEMTs with gold in source/drain features, then electrical connection is achieved, but contamination issues and manufacturing complexity increase
Solution Approach 1:
The patent removes gold from the source/drain feature composition entirely, extracting the harmful element while maintaining the electrical connection function through alternative materials (silicon and metal layers forming salicide structures). This eliminates gold contamination issues while preserving the essential electrical connectivity requirement.
Solution Approach 2:
The patent employs standard silicon and common metal layers that can be processed through conventional semiconductor fabrication techniques, replacing expensive gold with more economical materials that achieve the same electrical connection function without introducing contamination problems.
2Manufacturing precision
If conventional etching methods are used across semiconductor chip regions, then through holes are formed, but etching uniformity and electrical performance consistency deteriorate
Solution Approach 1:
The patent implements region-specific etching parameters and process conditions tailored to different semiconductor chip regions. By adjusting etching conditions locally for each region rather than applying uniform conditions across the entire wafer, the method achieves consistent through hole formation and electrical performance across all regions despite variations in material properties or processing conditions.
Solution Approach 2:
The patent modifies etching process parameters (such as etchant composition, temperature, pressure, or power) to optimize through hole formation across different chip regions. By dynamically adjusting these parameters based on regional requirements, the process achieves uniform etching results and consistent electrical performance throughout the semiconductor device.
3Reliability
If III-V semiconductor compound processes are used, then high electron mobility is achieved, but manufacturing flexibility and integration with silicon fabrication decrease
Solution Approach 1:
The patent combines III-V semiconductor compound processes with standard silicon fabrication techniques in an integrated manufacturing approach. By merging the high electron mobility benefits of III-V materials with the versatility and scalability of silicon fabrication processes, the method achieves both superior device performance and manufacturing flexibility, allowing the same process line to produce different device types and configurations.
Solution Approach 2:
The patent develops a universal fabrication process that can handle both III-V semiconductor compounds and silicon-based structures using the same equipment and methodology. This multi-functional approach enables the manufacturing system to produce various semiconductor devices with different material systems, increasing adaptability and reducing the need for specialized process lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of electrical performance across HEMT regions, reduces manufacturing costs, and increases flexibility in production by integrating III-V semiconductor processes with silicon-fabrication techniques, while ensuring reliable ohmic contacts and improved carrier channel control.
Implementation Method 1
A HEMT is a field effect transistor incorporating a junction between two materials with different band gaps (i.e., a heterojunction) as the channel
Implementation Method 2
the second III-V compound layer donates electrons to a carrier channel at an interface between the first III-V compound layer and the second III-V compound layer
Implementation Method 3
annealing the metal layer and the silicon feature to form a salicide source/drain feature
Data Source
AI summary
A high electron mobility transistor (HEMT) includes a first compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second compound layer between the salicide source feature and the salicide drain feature.