Sequential Access Memory for FECC Encoder Area Reduction
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Solution Overview
Problem
Existing implementations of Forward Error Correcting Codes (FECC) in FPGA and ASIC devices face significant memory area overhead due to the use of dual-port static RAM, which increases implementation costs and form factor, especially as block sizes increase, necessitating a more area-efficient memory solution.
Innovation Solution
Implementing Sequential Access Memory (SAM) instead of traditional RAM for memory blocks in FECC encoders and decoders, where data is accessed sequentially, reducing the need for bulky address decoding circuits and allowing for more efficient memory access, thereby minimizing memory area and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If dual-port static RAM is used for memory blocks in FECC encoders and decoders, then random access capability is provided, but memory area and implementation cost increase significantly
Solution Approach 1:
The patent extracts and removes the address decoding circuitry from the memory structure, retaining only the essential sequential access functionality. This eliminates the bulky address decoders that consume significant area in dual-port RAM implementations, while maintaining sufficient operational capability for FECC applications where sequential access patterns dominate.
Solution Approach 2:
The patent employs simplified memory structures that are area-efficient and optimized for the specific operational patterns of FECC codes. Rather than using full-featured dual-port RAM, the invention uses streamlined memory blocks that provide the necessary sequential access functionality at a fraction of the area cost, accepting that these memory structures are purpose-built for this specific application.
2Reliability
If larger block sizes are used in FECC codes, then error correction performance and data rates improve, but memory usage increases proportionally
Solution Approach 1:
The patent changes the fundamental parameter of memory access from random to sequential, which fundamentally alters the memory structure requirements. This parameter change enables the use of more area-efficient memory types that are optimized for sequential access patterns, thereby reducing memory area while maintaining the ability to handle larger block sizes for improved error correction performance.
3Adaptability or versatility
If dual-port static RAM with address decoders is implemented, then memory access flexibility is provided, but power consumption and area increase
Solution Approach 1:
The patent removes the power-intensive address decoding circuits from the memory implementation. By extracting this functionality, the invention significantly reduces power consumption while retaining the essential memory storage and sequential access capabilities needed for FECC operations, where the access patterns are sufficiently predictable to not require complex address decoding.
Data Source
AI summary
SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation to sequential accesses. According to the present invention, Forward Error Correcting Code encoder and decoder structures are shown to allow the use of SAM in their memory designs. Thus SAM is utilized in FECC implementations to achieve better area efficiency for the same amount of memory as well as higher throughput for the hardware implementations.