Same-Bank Memory Row EDC Storage for Low-Power Error Correction
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Solution Overview
Problem
Existing DRAM systems face challenges in managing computational errors due to manufacturing variations, operational stresses, and electrical interference, leading to undesirable errors and memory failures, which current error detection and correction methods are inefficient in addressing.
Innovation Solution
A memory system is designed to logically divide memory rows into separate regions for data storage and error detection and correction (EDC) codes, allowing simultaneous access to both within the same bank, thereby reducing power consumption and avoiding bank conflicts, while utilizing local controllers to remap addresses and perform error correction and decryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction codes are stored in separate memory banks, then error correction capability is maintained, but power consumption increases and bank conflicts occur
Solution Approach 1:
The patent combines data and error detection/correction codes into the same memory bank by dividing the memory row into a data region and an EDC code region. This merging eliminates the need to access separate banks for EDC operations, thereby reducing power consumption and avoiding bank conflicts while maintaining full error correction capability.
Solution Approach 2:
The patent segments each memory row into distinct functional regions: a data region for storing computational data and an EDC code region for storing error detection and correction codes. This segmentation allows both data and EDC codes to coexist in the same bank, enabling simultaneous access without interference and resolving the contradiction between reliability and power efficiency.
2Reliability
If error detection and correction codes are stored in separate memory banks, then error correction capability is maintained, but access latency increases due to bank conflicts
Solution Approach 1:
By merging data and EDC codes into the same memory bank, the system enables simultaneous access to both during read operations. This eliminates bank conflicts that would otherwise cause access latency, as the memory controller can retrieve both data and EDC codes in a single bank access operation.
Solution Approach 2:
The segmentation of each row into data and EDC code regions allows the memory controller to selectively access only the necessary portions during read operations. This targeted access approach reduces latency by avoiding unnecessary memory bank switches and conflicts.
3Reliability
If traditional error detection and correction methods are used, then computational errors are managed, but power consumption increases
Solution Approach 1:
The patent merges the EDC code storage with data storage in the same memory bank, allowing the memory system to manage computational errors without requiring separate bank accesses. This integration significantly reduces the power consumption associated with error detection and correction operations compared to traditional methods.
Data Source
AI summary
A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.