Semiconductor Layout With Same-Level Peripheral Circuits for Area Reduction
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Solution Overview
Problem
The increasing demand for high performance, high speed, and multifunctionality in semiconductor devices necessitates finer patterns and reduced sizes, which poses challenges in integrating semiconductor devices with fine widths and spacing distances.
Innovation Solution
A semiconductor device design that includes a memory cell region and a peripheral circuit region at the same level or layer, with specific structural configurations such as overlapping channel structures, bitlines, and gate electrodes, allowing for reduced area usage by integrating peripheral circuit regions within the same horizontal and vertical dimensions as memory cell regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If peripheral circuit regions are disposed at the same level as memory cell regions, then device area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking channel structures in the vertical direction while maintaining peripheral and memory cell regions at the same horizontal level. This three-dimensional arrangement reduces the horizontal footprint of the device without significantly increasing manufacturing complexity, as the stacked structures can be formed using standard vertical deposition and etching processes.
Solution Approach 2:
The device is segmented into distinct functional regions (memory cell region and peripheral circuit region) that are horizontally separated but vertically aligned. This segmentation allows independent optimization of each region while maintaining compact overall device area, as each region can be manufactured using region-specific process parameters.
2Productivity
If fine patterns are implemented to increase integration density, then device functionality is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional stacked channel structures. This vertical stacking increases the effective channel area and integration density without requiring proportionally finer lateral patterning, thereby improving productivity while moderating the increase in manufacturing precision requirements.
3Area of stationary object
If device size is reduced to meet integration demands, then area efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements nested structures where gate electrodes surround channel structures in a gate-all-around configuration, and stacked channel structures are vertically nested within the same horizontal footprint. This nesting maximizes the use of available space, reducing device size while the modular nature of the nested structures keeps manufacturing complexity manageable through repeated use of standard fabrication steps.
Data Source
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AI summary
A semiconductor device includes a memory cell region (CA) and a peripheral circuit region (PERI1) adjacent the memory cell region (CA) in a first horizontal direction (X). The memory cell region (CA) includes cell channel structures extending in the first horizontal direction (X) and spaced apart from each other in a vertical direction (Z); a cell bitline (BL) extending in the vertical direction (Z); and cell gate electrodes overlapping the cell channel structures in the vertical direction (Z) and extending in a second horizontal direction (Y). The peripheral circuit region (PERI1) includes a peripheral channel structure extending in the first horizontal direction (X); a peripheral bitline extending in the vertical direction (Z); and a first peripheral gate electrode and a second peripheral gate electrode overlapping the peripheral channel structure in the vertical direction (Z) and extending in the second horizontal direction (Y). At least one of the cell channel structures is at a same level as the peripheral channel structure in the vertical direction (Z).