Sample Clock Correction for Wireless Transceivers

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Solution Overview

Problem

In wireless radio transceiver systems, timing drift between the radio transceiver system and user equipment can lead to decreased communication quality, disruption, or failure due to inaccuracies in the reference clock frequency, which may cause user equipment to self-correct and become desynchronized with other systems.

Innovation Solution

A sample clock correction unit is implemented to adjust the clock frequency by inserting or removing samples at frame boundaries in the transmission and reception data streams, ensuring synchronization with the desired clock frequency and maintaining communication integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the reference clock frequency is not accurately generated, then timing drift occurs between radio transceiver system and user equipment, but increasing clock accuracy requirements increases system complexity and cost

Engineering Contradiction:
Improveclock frequency accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a sample insertion/removal mechanism as an intermediary component between the clock source and data processing stages. This mediator compensates for timing drift by adjusting sample timing without requiring high-precision clock hardware, thus resolving the contradiction between timing accuracy and system complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter of sample timing by inserting or removing samples at frame boundaries. This parameter adjustment compensates for clock frequency inaccuracies and timing drift, achieving accurate timing synchronization without requiring precise clock generation

Inventive Principle:
Principle #35Parameter changes

2Reliability

If user equipment corrects timing drift by adjusting internal timing, then synchronization with the radio transceiver system is improved, but desynchronization with other systems occurs

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidsystem compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies preliminary action by correcting timing drift at the radio transceiver system side before data transmission, rather than allowing user equipment to perform self-correction. This preliminary correction ensures that all receiving systems receive properly synchronized data, maintaining both communication reliability and system compatibility

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by monitoring clock frequency accuracy and timing drift, then automatically adjusting sample timing through insertion or removal. This closed-loop feedback mechanism maintains synchronization without requiring user equipment to adapt, preserving compatibility across multiple systems

Inventive Principle:
Principle #23Feedback

3Measurement precision

If samples are inserted or removed to correct timing drift, then clock frequency accuracy is improved, but data stream structure complexity increases

Engineering Contradiction:
Improvetiming accuracyVSAvoiddata processing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the data stream into frames with clear boundaries, and performs sample insertion or removal only at these frame boundaries. This segmentation approach simplifies the correction process by confining complex operations to specific locations, reducing overall data processing complexity while maintaining timing accuracy

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9979502B2Apparatus and method for sample clock correction
Publication Date: 2018.05.22 KEYSIGHT TECH SINGAPORE (SALES) PTE LTD
  • US9979502B2 patent drawing
  • US9979502B2 patent drawing
  • US9979502B2 patent drawing

AI summary

A radio transceiver apparatus configured to transmit and receive radio frequency signals, the apparatus comprising, a sample clock configured to generate samples at a clock frequency fs, a processor configured to generate a transmission data stream signal, wherein the transmission data stream signal comprises frames separated by frame boundaries between the frames, and wherein the frames are comprised of at least one sample, and a sample clock correction unit, wherein in a first transmission configuration when the clock frequency fs is greater than a desired clock frequency fr, the sample clock correction unit is configured to insert at least one sample into at least one frame boundary between frames, or in a second transmission configuration when the clock frequency fs is less than a desired clock frequency fr, the sample clock correction unit is configured to remove at least one sample from at least one frame boundary between the frames.