Sample-and-Hold Circuit With Boost Capacitors for Fast Charging

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional sample-and-hold circuits face challenges in supplying high currents to charge the sampling capacitor quickly, leading to time delays that are unacceptable in various applications, especially when the driver amplifier is unable to provide sufficient current.

Innovation Solution

The implementation of a boost circuit with two or more capacitors in parallel, which stores the full charge required by the sampling capacitor during the holding phase, allowing the boost capacitors to instantly charge the sampling capacitor when switched, reducing the need for the driver amplifier to supply high currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the driver amplifier directly charges the sampling capacitor during the sampling phase, then the sampling capacitor can be charged, but the driver amplifier must supply substantial current which causes time delay in the output signal slew

Engineering Contradiction:
Improvecharging speed of sampling capacitorVSAvoidpeak current requirement of driver amplifier
Core Design Contradiction:
SpeedVSPower

Solution Approach 1:

The patent applies preliminary action by pre-charging the transfer capacitor during the holding phase before the sampling phase begins. This allows the transfer capacitor to store the full charge required by the sampling capacitor in advance, so that during the sampling phase, the pre-charged transfer capacitor can instantly transfer its charge to the sampling capacitor without requiring the driver amplifier to supply high current at that moment.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If the driver amplifier supplies high current to charge the sampling capacitor quickly, then the charging speed increases, but the amplifier output signal takes time to slew which causes unacceptable delay

Engineering Contradiction:
Improvetime delay in sampling processVSAvoidcurrent supply capability of driver amplifier
Core Design Contradiction:
Loss of timeVSPower

Solution Approach 1:

The patent introduces a transfer capacitor as an intermediary between the driver amplifier and the sampling capacitor. This transfer capacitor acts as a charge buffer that can be pre-charged during the holding phase and then instantly discharge its stored charge to the sampling capacitor during the sampling phase, eliminating the need for the driver amplifier to supply high current during sampling and thus avoiding slew-induced delays.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Power

If pre-charge capacitors are used to store charge during the holding phase, then part of the charge required by the sampling capacitor can be provided, but current spikes are still demanded from the driver amplifiers when the sampling capacitors are switched

Engineering Contradiction:
Improvecharge storage capability during holding phaseVSAvoidcharging speed of sampling capacitor
Core Design Contradiction:
PowerVSSpeed

Solution Approach 1:

The patent changes the operational parameters by using a single transfer capacitor that is fully charged to the full voltage swing required by the sampling capacitor, rather than using multiple pre-charge capacitors charged to partial voltages. This full-charging approach ensures that when the transfer capacitor connects to the sampling capacitor, it can provide the complete required charge instantly, eliminating current spikes from the driver amplifier while achieving fast charging.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution significantly reduces the peak current requirement on the input driver, allowing for faster charging of the sampling capacitor and minimizing delays caused by amplifier output slewing, resulting in a more efficient and faster sampling process.

Implementation Method 1

a sampling capacitor configured to receive the output signal through the sampling switch when the sampling switch is closed; a boost circuit configured to receive the output signal independent of whether the sampling switch is closed or open and to be in parallel with the sampling capacitor when the sampling switch is closed

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8581636B2Sample-and-hold circuit arrangement
Publication Date: 2013.11.12 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US8581636B2 patent drawing
  • US8581636B2 patent drawing
  • US8581636B2 patent drawing

AI summary

Sample-and-hold circuits typically operate at maximum speed when the sampling phase is much shorter than the holding phase. Thus, a device driving the sampling capacitor is disconnected most of the time. Methods and apparatus use the holding phase to store the full charge required by the sampling capacitor to track the amplifier output in at least two “boost” capacitors configured such that when the sampling capacitor is switched to the driver, the boost capacitors are also switched to the driver. Thus, the sampling capacitor is almost instantly charged to the required voltage, and the driver needs to supply only any remaining “error” charge, avoiding delays due to driver output slewing.