Sample-and-Hold Circuit Using Capacitive Feedback for Noise Reduction

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Solution Overview

Problem

Conventional sample and hold circuits introduce noise due to the switching of the floating diffusion node in CMOS imaging arrays, which cannot be effectively reduced by increasing the size of the storage capacitor without exceeding the available circuit area.

Innovation Solution

A sample and hold circuit design utilizing first and second switches, and first, second, and third capacitors, along with an amplifier, where the amplifier acts as a capacitive transimpedance amplifier with the third capacitor as feedback when the first switch is non-conducting and the second switch is conducting, effectively transferring noise to the third capacitor and reducing it from the signal storage capacitor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a large storage capacitor is used in the sample and hold circuit, then the noise from switch opening is reduced, but the circuit area increases beyond available space

Engineering Contradiction:

Improvenoise from switch openingVSAvoidcircuit area

Core Design Contradiction:

Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The storage capacitor is divided into two separate capacitors (first storage capacitor and second storage capacitor) that work together in a correlated double sampling configuration. This segmentation allows noise reduction through differential measurement while keeping individual capacitor sizes small enough to fit within the available circuit area.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A third capacitor is introduced as a feedback element in the transimpedance amplifier configuration. This intermediary capacitor helps transfer and cancel noise between the two storage capacitors, reducing the overall noise impact without requiring larger capacitor sizes.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If correlated double sampling is used to reduce reset noise, then reset potential variations are reduced, but a new noise source is introduced from the sample and hold circuit switching

Engineering Contradiction:

Improvereset potential variationsVSAvoidnoise from sample and hold switching

Core Design Contradiction:

Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The noise generated by the switch opening in the sample and hold circuit is converted into a beneficial signal by using it to cancel corresponding noise in the correlated double sampling measurement. The noise from switching the first storage capacitor is used to offset noise in the second storage capacitor, transforming a harmful effect into a noise-cancellation mechanism.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The third capacitor is configured as a feedback element in the transimpedance amplifier, creating a feedback path that transfers noise signals between the two storage capacitors. This feedback mechanism enables the system to automatically cancel noise by comparing and subtracting the noise signals from both capacitors.

Inventive Principle:

Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design achieves a significant reduction in noise power while maintaining the same total capacitor area, with noise power reduced by a factor of approximately 90 when C2 is set to 0.1*C0 and C is set to 0.9*C0, without increasing the circuit area.

Implementation Method 1

The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8952729B2Sample and hold circuit with reduced noise

Publication Date: 2015.02.10 FAIRCHILD IMAGING INC

AI summary

A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.