Sample-and-Hold Circuit Timing for Charge Injection Cancellation
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Solution Overview
Problem
The provision of a switch for cancellation in a semiconductor circuit to address charge injection and clock feedthrough causes power supply noise to propagate to the subsequent circuit stage during the hold of a bias voltage.
Innovation Solution
A semiconductor circuit design incorporating a first transistor for sample and hold, a second transistor for cancellation, and a third transistor for short-circuiting or isolating nodes, with the second transistor's gate waveform opposite in phase to the first transistor's, and the third transistor transitioning after the second transistor, to mitigate potential fluctuations and power supply noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a switch for cancellation is provided to address charge injection and clock feedthrough, then potential fluctuations are canceled, but power supply noise propagates to the subsequent circuit stage
Solution Approach 1:
A third transistor is introduced as an intermediary switching element between the cancellation switch and the subsequent circuit stage. This third transistor acts as a mediator that controls the connection timing to prevent noise propagation while maintaining the cancellation function. The third transistor switches off after the cancellation switch, creating a noise isolation barrier that blocks power supply noise from reaching the subsequent stage.
2Stability of the object's composition
If a switch for sample and hold is provided, then bias voltage can be held stable, but charge injection and clock feedthrough cause potential fluctuations
Solution Approach 1:
The cancellation switch is designed to activate before the sample and hold switch turns off, and remains active for a period after the sample and hold switch transitions. This preliminary anti-action cancels the charge injection and clock feedthrough effects that occur when the sample and hold switch changes state, by providing an opposing charge compensation mechanism through the cancellation switch.
Solution Approach 2:
The cancellation switch is turned on in advance before the sample and hold switch transitions, preparing the cancellation mechanism to counteract the upcoming charge injection and clock feedthrough. By establishing the cancellation path beforehand, the system is ready to immediately compensate for any potential fluctuations when the sample and hold switch changes state.
3Reliability
If the second transistor switches immediately when the first transistor turns off, then charge injection is canceled, but power supply noise affects the subsequent circuit
Solution Approach 1:
The switching operation is divided into distinct periodic phases: first the sample and hold switch transitions, then the cancellation switch activates to cancel charge injection, and finally the third transistor switches off to isolate the subsequent circuit. This periodic sequencing of switching actions ensures that each function (sampling, cancellation, isolation) occurs in the appropriate time window, preventing noise propagation while maintaining cancellation effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses potential fluctuations and power supply noise, maintaining stable voltage levels in the circuit by canceling charge injection and clock feedthrough effects.
Implementation Method 1
a bias voltage may fluctuate due to charge injection or clock feedthrough
Implementation Method 2
a bias voltage may fluctuate due to charge injection or clock feedthrough
Implementation Method 3
a third transistor that switches whether the first node and a second node are to be electrically short-circuited or cut off from each other
Data Source
AI summary
Provided is a semiconductor circuit that includes a first transistor that switches whether to acquire an input signal into a first node, a second transistor having at least one of a source and a drain that are connected to the first node, and a third transistor that switches whether the first node and a second node are to be electrically short-circuited or cut off from each other, wherein the state of the second transistor makes a transition to have a gate waveform opposite in phase to the gate waveform of a first transistor after the timing of a transition of the first transistor from an on-state to an off-state, and the third transistor makes a transition from an on-state to an off-state after the timing of the state transition of the second transistor.