Sample-and-Hold Countersoak Circuit for Dielectric Absorption
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Solution Overview
Problem
Dielectric absorption in capacitive sample-and-hold systems causes deviations in output voltage due to charge trapping, leading to crosstalk between channels, especially in multiplexed applications, and existing techniques struggle to effectively cancel this effect across varying temperatures.
Innovation Solution
A successive-approximation ADC with a DA-suppressing circuit that includes a countersoak phase after the conversion phase, where a second average voltage negatively correlated with the first average voltage is applied to the capacitors, using exclusive OR gates and latches to control switches, effectively canceling out dielectric absorption without significant timing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a hold capacitor is used in a sample-and-hold system, then the capacitor can maintain voltage during the hold phase, but dielectric absorption causes charge trapping that creates memory effects and crosstalk between samples
Solution Approach 1:
The patent applies preliminary anti-action by introducing a countersoak phase before the hold phase where a negative voltage is applied to the capacitor. This pre-conditioning step actively counteracts the dielectric absorption effect by releasing trapped charges before they can cause crosstalk during the subsequent hold phase, thereby eliminating the harmful memory effect while preserving the capacitor's ability to maintain voltage.
2Measurement precision
If the track time is increased relative to hold time to reduce dielectric absorption memory, then sample-to-sample memory decreases, but the sampling rate must be reduced significantly
Solution Approach 1:
The patent applies preliminary action by performing the countersoak operation in a dedicated phase before the hold phase begins. This preliminary step resets the capacitor's dielectric state, allowing the subsequent hold phase to proceed with minimal memory effects regardless of its duration. The sampling rate can thus be maintained at high values without compromising accuracy, as the harmful memory effect is eliminated in advance rather than being suppressed by extending track time.
3Reliability
If existing DA cancellation techniques are used, then some reduction in dielectric absorption effect may be achieved, but the techniques fail to effectively cancel the effect across varying temperatures
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the countersoak voltage magnitude based on the held voltage level. The system monitors the voltage held on the capacitor and applies a correspondingly scaled negative voltage during the countersoak phase. This adaptive approach ensures effective cancellation across varying temperatures and operating conditions, as the cancellation strength automatically matches the actual dielectric absorption effect rather than relying on fixed predetermined values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The countersoak phase allows for efficient cancellation of dielectric absorption effects, maintaining accuracy across temperatures without requiring knowledge of the DA effect's magnitude, thus reducing crosstalk and maintaining system performance.
Implementation Method 1
an array of capacitors (201) controllable to store a voltage value
Implementation Method 2
Dielectric absorption (DA) is a form of capacitor non-ideality wherein the capacitor has additional memory of its history
Data Source
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AI summary
Sample-and-hold (S/H) circuitry operating in track and hold phases and having a first S/H circuit with a first hold capacitor at which a first voltage value is maintained in the hold phase, and a dielectric absorption (DA)- suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in an additional phase after completing the hold phase and before entering the track phase. The DA-suppressing circuit is configured to supply the first hold capacitor, during an operation in the additional phase, with a second voltage value that is negatively correlated with the first voltage value.