Multiplexed Sample-and-Hold Circuit With Feedback Leakage Suppression

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Solution Overview

Problem

Sample and hold circuits face significant leakage issues during hold intervals, especially when signals need to be held for long periods at high precision, leading to errors in signal processing.

Innovation Solution

A signal processing circuit with a first and second sample and hold circuit, where the voltage feedback amplifier increases the effective resistance of the input switch by a factor of at least 100, using a series switch configuration and a voltage feedback switch to minimize leakage, and a clock circuit to control the switches and amplify signals effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional sample and hold circuit is used, then the circuit structure is simple, but leakage through the input switch causes significant error during long hold intervals

Engineering Contradiction:
Improvesignal holding accuracyVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements voltage feedback from the hold capacitor back to the input switch through a feedback amplifier. This feedback mechanism dynamically compensates for leakage current by adjusting the switch control voltage, thereby maintaining signal accuracy during extended hold intervals without requiring excessively complex circuitry

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The input switch is divided into multiple segments (first switch, second switch, third switch) with separate control. This segmentation allows independent optimization of each switch's function - some switches handle signal routing while others are dedicated to leakage compensation, improving overall holding accuracy while keeping individual switch complexity manageable

Inventive Principle:
Principle #1Segmentation

2Duration of action of stationary object

If the hold interval is extended for long period signal holding, then the signal can be maintained longer, but leakage error increases significantly

Engineering Contradiction:
Improvehold interval durationVSAvoidsignal holding precision
Core Design Contradiction:
Duration of action of stationary objectVSMeasurement precision

Solution Approach 1:

The feedback amplifier continuously monitors the hold capacitor voltage and adjusts the input switch control accordingly. This closed-loop control counteracts leakage effects that accumulate over time, enabling accurate signal holding over extended intervals by dynamically compensating for precision-degrading leakage current

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent transitions from static switch control to dynamic control where the input switch characteristics are continuously adjusted based on feedback. This dynamic adaptation allows the circuit to maintain precision throughout the hold interval by responding to changing leakage conditions in real-time

Inventive Principle:
Principle #15Dynamics

3Reliability

If the input switch resistance is increased to reduce leakage, then leakage is reduced, but signal charging during sampling interval becomes slower

Engineering Contradiction:
Improveleakage reductionVSAvoidsignal charging speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The input path is segmented into multiple switches with different resistance characteristics. The first switch provides low resistance for rapid signal charging during the sampling phase, while the second and third switches are optimized for high resistance to minimize leakage during the hold phase. This segmentation resolves the speed-leakage tradeoff by assigning different functions to different segments

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs periodic switching where the input switches are closed during sampling intervals to rapidly charge the hold capacitor, then opened during hold intervals to minimize leakage. This periodic operation allows the circuit to alternate between low-resistance (fast charging) and high-resistance (low leakage) states, achieving both speed and leakage reduction at different times in the cycle

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11881851B1Multiplexing sample-and-hold circuit
Publication Date: 2024.01.23 HRL LAB
  • US11881851B1 patent drawing
  • US11881851B1 patent drawing
  • US11881851B1 patent drawing

AI summary

A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.