Sample-and-Hold Interface Circuit with Dynamic Voltage Divider
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Solution Overview
Problem
Existing sample-and-hold circuits face issues when interfacing chips with different working voltages, leading to signal attenuation, increased power consumption, and reduced signal/noise ratio due to the use of voltage dividers, which also shorten the sampling time and unnecessarily attenuate both writing and reading voltages.
Innovation Solution
A sample-and-hold interface circuit incorporating a pair of serial resistors, a Switched-OP, a PMOS transistor, and a timing circuit, where the PMOS transistor controls the voltage divider to be open-circuit when only the reading voltage is input, reducing power consumption and maintaining the signal/noise ratio by preventing unnecessary attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage divider is used to attenuate the input signal to protect the Switched-OP, then the Switched-OP is protected from voltage damage, but power consumption increases due to extra current requirement
Solution Approach 1:
The patent applies dynamics by making the voltage divider configurable through a switch. The voltage divider is connected only when needed (when input voltage exceeds 3.3V), and disconnected otherwise. This dynamic connection allows the system to protect the Switched-OP when necessary while avoiding continuous power consumption from the voltage divider circuit.
2Reliability
If a voltage divider is used to attenuate the input signal, then the Switched-OP is protected, but the sampling time is reduced due to longer setup time
Solution Approach 1:
The patent makes the voltage divider dynamically connectable and disconnectable. When the input voltage is within the safe range (≤3.3V), the voltage divider is disconnected, eliminating the setup time delay and allowing immediate sampling. When protection is needed, the voltage divider connects temporarily to protect the Switched-OP, then disconnects once protection is no longer required.
3Reliability
If a voltage divider is used to attenuate the input signal, then the Switched-OP is protected, but the signal/noise ratio decreases due to unnecessary attenuation of reading voltage
Solution Approach 1:
The patent dynamically controls the voltage divider connection based on input voltage conditions. When the input is a reading voltage (≤3.3V), the voltage divider is disconnected, allowing the reading voltage to pass through without attenuation, thus maintaining the signal/noise ratio. When the input is a writing voltage (>3.3V), the voltage divider connects to protect the Switched-OP.
4Reliability
If a voltage divider is used to attenuate the input signal, then the Switched-OP is protected, but both writing and reading voltages are unnecessarily attenuated
Solution Approach 1:
The patent makes the voltage divider dynamically connectable and disconnectable based on input voltage conditions. The voltage divider connects only when the input voltage exceeds 3.3V (writing voltage), and disconnects when the input voltage is within the safe range (reading voltage). This dynamic behavior allows the circuit to protect the Switched-OP from writing voltages while preserving the integrity of reading voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces power consumption and enhances the signal/noise ratio by only attenuating the writing voltage, while ensuring the safety of the Switched-OP with a lower working voltage, thereby improving the operational efficiency of the sample-and-hold function.
Implementation Method 1
The PMOS transistor works as the switch of the voltage divider. When the PMOS transistor is on, the pair of the resistors in serial work as a voltage divider. When the PMOS transistor is off, the pair of the resistors in serial is open-circuit.
Implementation Method 2
A voltage divider, comprising a first resistor 1 and a second resistor 2, is used to attenuate an input signal of a sample-and-hold circuit 3 down to the level lower than 3.3V to prevent this problem.
Implementation Method 3
The Switched-OP provides a sample-and-hold function. The timing circuit is used to control the on and off of the PMOS, and the timing for the Switched-OP to sample and hold.
Data Source
AI summary
A sample-and-hold interface circuit of a pickup head uses a circuit switch to control a voltage divider. When the circuit switch receives a signal Break, a voltage divider does not consume extra power to decrease the driving power consumption of a pickup head. And a controller can sample an unattenuated input signal to increase the signal/noise ratio.