Cross-Coupled Sample-and-Hold Layout for Low-Parasitic Sampling
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Solution Overview
Problem
Track and hold circuits in analog-to-digital converters face challenges due to significant channel charge injection and channel conductance changes, which affect the sampling of high-speed analog signals, leading to parasitic capacitance and resistance issues that limit operating speed and introduce signal attenuation.
Innovation Solution
A sample and hold circuit design incorporating cross-coupled switches with dummy transistors that are not electrically connected to metal lines, minimizing parasitic capacitance and resistance, and using a layout arrangement where dummy transistors are placed in the front-end of line (FEOL) region without via connections to the back-end of line (BEOL) region, thereby reducing feed-through and signal attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dummy transistors are electrically connected to metal lines to compensate for channel charge injection and conductance changes, then the sampling accuracy is improved, but parasitic capacitance and resistance increase, limiting operating speed
Solution Approach 1:
The patent extracts the dummy transistors from the electrical connection to metal lines, isolating them in the FEOL region without via connections to BEOL. This removes the parasitic capacitance and resistance associated with via connections while preserving the dummy transistors' ability to compensate for channel charge injection and conductance changes, thus maintaining sampling accuracy without sacrificing operating speed.
Solution Approach 2:
The patent introduces an intermediary layout arrangement where dummy transistors are placed in the FEOL region but electrically isolated from BEOL metal lines. This intermediary configuration allows the dummy transistors to serve their compensation function through capacitive coupling and electrical field effects without the harmful parasitic effects of direct via connections.
2Reliability
If via connections are used to connect dummy transistors to metal lines, then electrical connection is achieved, but feed-through and signal attenuation increase
Solution Approach 1:
The patent removes the via connections that create feed-through and signal attenuation problems. By extracting the dummy transistors from the BEOL metal line connections and placing them solely in the FEOL region without via holes, the design eliminates the harmful feed-through effects and signal attenuation while maintaining sufficient electrical connection through alternative capacitive coupling mechanisms.
3Ease of manufacture
If standard layout arrangement with via connections is used, then manufacturing process is simplified, but parasitic capacitance and resistance limit high-speed operation
Solution Approach 1:
The patent applies local quality by creating a specialized layout arrangement for dummy transistors in the FEOL region with distinct electrical isolation properties. Instead of uniformly connecting all transistors to metal lines via vias, the dummy transistors are locally configured without via connections to BEOL, creating a local quality difference that reduces parasitic effects in critical high-speed signal paths while maintaining standard manufacturing processes.
Data Source
AI summary
A sample and hold circuit may include: a first transistor connected between a first input terminal configured to receive a first input signal and a first output terminal configured to output a first sampled signal; a second transistor connected between a second input terminal configured to receive a second input signal and a second output terminal configured to output a second sampled signal; a first dummy transistor provided between the first input terminal and the second output terminal; and a second dummy transistor provided between the second input terminal and the first output terminal. A source region and a drain region of the first dummy transistor and a source region and a drain region of the second dummy transistor may not be electrically connected to a metal line connecting the first transistor with the second transistor.