Sample-and-Hold Amplifier Using Negative Capacitance for ADC Linearity
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Solution Overview
Problem
High-speed analog-to-digital converters face linearity limitations due to mismatches among channels, especially when using time-interleaved architectures, which degrade performance and reduce spurious-free dynamic range.
Innovation Solution
A sample and hold amplifier is designed with a cascaded configuration of filter capacitors and non-Forster circuits, incorporating equivalent negative capacitors to cancel internal parasitic capacitors, improving linearity and stability by pushing non-dominant poles to higher frequencies without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved architectures are used to improve sampling speed, then sampling rate is improved, but channel mismatches worsen leading to degraded linearity
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitors into a beneficial effect by introducing negative capacitors that cancel them out. The parasitic capacitors cause linearity degradation, but by adding negative capacitors with equal magnitude but opposite sign, the harmful capacitance is neutralized and the system achieves improved linearity (>75 dB) while maintaining high sampling rates
Solution Approach 2:
The patent changes the electrical parameters of the circuit by introducing negative capacitance values where positive capacitance normally exists. This parameter transformation allows the system to push non-dominant poles to higher frequencies, improving both linearity and stability margins without sacrificing sampling speed
2Device complexity
If traditional sample and hold amplifiers are used, then circuit simplicity is maintained, but linearity is limited affecting ADC performance
Solution Approach 1:
The patent segments the sample and hold amplifier into multiple stages, each with its own negative capacitor for parasitic cancellation. This multi-stage architecture allows progressive improvement of linearity while keeping each individual stage relatively simple, achieving overall linearity >75 dB through cumulative effect of multiple cancellation stages
3Manufacturing precision
If loop gain is increased to improve linearity, then linearity is improved, but stability worsens due to reduced phase margin
Solution Approach 1:
The patent changes the frequency parameters of the system by pushing non-dominant poles to higher frequencies through negative capacitance. This parameter shift allows the system to achieve both high loop gain (for linearity) and adequate phase margin (for stability) simultaneously, resolving the traditional trade-off between these two parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves improved linearity beyond 75 dB and faster stability, optimizing the trade-off between loop gain and phase margin, enhancing the performance of high-speed analog-to-digital converters.
Implementation Method 1
The first-stage non-Forster circuit and the second-stage non-Forster circuit cancel an internal parasitic capacitor by utilizing an equivalent negative capacitor for improved linearity and faster stability
Data Source
AI summary
The present disclosure relates to a sample and hold amplifier, a high-speed analog-to-digital converter, and an electronic device. The sample and hold amplifier, the high-speed analog-to-digital converter, and the electronic device are provided in the present disclosure. By arranging a first-stage non-Forster circuit and a second-stage non-Forster circuit in the sample and hold amplifier, and by using a negative capacitor to cancel out an internal parasitic capacitor, the first-stage non-Forster circuit and the second-stage non-Forster circuit may reduce nonlinear distortion caused by the parasitic capacitor and improve the linearity of the sample and hold amplifier. In addition, the first-stage non-Forster circuit focuses on providing preliminary gain and parasitic capacitor compensation, ensuring that the circuit may effectively process an input signal and reduce an impact of non-dominant poles on overall performance. The second-stage non-Forster circuit further optimizes gain and stability, thereby enabling the sampling and holding circuit to achieve faster stability overall.