Sample-and-Hold Phase Detector for Low-Jitter Clock Recovery
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Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits face challenges in maintaining low jitter generation, especially when dealing with stressful data patterns and pathological patterns within the CDR loop bandwidth, as they are sensitive to input data jitter and bit patterns, leading to phase variations in the recovered clock signal and increased susceptibility to noise and component mismatches.
Innovation Solution
A linear sample and hold phase detector is introduced, coupled with a linear phase difference generator and sample and hold circuit, which generates phase difference signals for rising and falling edges of the input data signal, and a gain block non-linearizes the phase information to improve phase correction and reduce jitter, preventing the circuit from entering a tri-state mode and maintaining correction even without data transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR circuits are used to extract clock from input data stream, then the recovered clock phase is susceptible to variation, but meeting jitter generation requirements in frequency bands both above and below loop bandwidth is difficult
Solution Approach 1:
The phase detection function is segmented into two independent paths: one path detects phase difference at rising edges of input data, and another path detects phase difference at falling edges. This segmentation allows the circuit to measure phase differences at both edges separately, providing more comprehensive phase information for correction while maintaining low jitter generation across different frequency bands.
Solution Approach 2:
Sample and hold circuits are introduced as intermediary elements that capture and store the phase difference measurements from both rising and falling edges. These intermediaries maintain the phase difference information through periods without data transitions, enabling continuous phase correction and improving reliability for meeting jitter requirements.
2Reliability
If the circuit operates with stressful data patterns for long periods, then the recovered clock phase varies, but the circuit may enter tri-state mode and lose correction capability
Solution Approach 1:
The sample and hold circuits ensure continuous phase correction by maintaining the phase difference measurements even when no data transitions occur. This continuity prevents the circuit from entering a tri-state mode where correction capability is lost, ensuring reliable operation during long periods of stressful data patterns.
Solution Approach 2:
The phase difference information is sampled and held in advance during data transitions, preparing the correction signal before periods without transitions occur. This preliminary action ensures that phase correction can continue without interruption even when the input data remains static for extended periods.
3Measurement precision
If conventional phase detectors are used, then the circuit is sensitive to input data jitter and bit patterns, but component mismatches and non-ideal behavior increase susceptibility to noise
Solution Approach 1:
The phase difference measurements from both rising edges and falling edges are merged and combined to produce the final phase correction signal. This merging approach averages out the effects of component mismatches and non-ideal behaviors, reducing noise susceptibility while maintaining high measurement precision.
Solution Approach 2:
The circuit measures phase differences at two different parameters (rising edges and falling edges) rather than relying on a single measurement point. This parameter change provides redundant information that compensates for component variations and reduces sensitivity to noise and mismatches.
Data Source
AI summary
Linear sample and hold phase detectors are disclosed herein. An example phase detector is coupled to an input data signal and a recovered clock signal and includes a linear phase difference generator circuit and a sample and hold circuit. The linear phase difference generator includes a first input coupled to the input data signal and a second input coupled to the recovered clock signal and outputs a first phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal and a second phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal. The sample and hold circuit is coupled to the first and second phase difference output signals and samples the voltage levels thereof in response to a first transition of the input data signal and holds the sampled voltage levels until a second transition of the input data signal. Novel clocking circuits using the linear sample and hold phase detector, as well as other types of linear phase detectors, are also disclosed herein in which a gain block non-linearizes the linear phase difference information output from the linear phase detector circuits.