Sample-and-Hold Precharging to Reduce AD Conversion Errors
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Solution Overview
Problem
In signal processing devices used for converting sine wave signals from rotation angle sensors into digital signals, reducing the capacitance of capacitor C1 in the filter circuit to minimize phase delay leads to increased charge sharing between capacitor C1 and capacitor C2, resulting in longer charge times and delayed output voltages, which causes errors in AD conversion when sampling occurs before the output voltage reaches the input voltage.
Innovation Solution
A signal processing device is designed with a filter circuit, a sample-and-hold circuit, an AD conversion circuit, and a control unit that applies a predetermined voltage to the second capacitor in the sample-and-hold circuit, charging it before sampling the analog signal that has passed through the filter circuit, thereby reducing the charge time of capacitor C1 and minimizing errors in digital signal conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the capacitance of capacitor C1 is reduced to reduce phase delay, then angle detection speed is improved, but the charge time of capacitor C1 increases causing AD conversion errors
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitor C2 to a specific voltage (1/2 of the reference voltage) before the sampling operation. This preliminary charging ensures that when C1 and C2 share charges during sampling, the voltage change on C1 is minimized, allowing the filter output to reach the input voltage quickly without causing AD conversion errors, thus resolving the contradiction between fast angle detection and accurate conversion.
2Measurement precision
If the sample-and-hold circuit samples after capacitor C2 charges are emptied, then sampling accuracy is improved, but capacitor C1 charge time increases
Solution Approach 1:
The patent reverses the conventional approach by pre-charging capacitor C2 before sampling instead of letting it empty first. By charging C2 to 1/2 of the reference voltage in advance, the subsequent charge sharing during sampling causes minimal voltage change on C1, allowing both fast charging and accurate sampling to coexist.
Solution Approach 2:
The patent changes the voltage parameter of capacitor C2 from 0V (empty state) to 1/2 of the reference voltage (pre-charged state) before sampling. This parameter change ensures that during charge sharing, the voltage change on C1 is minimized, allowing the system to maintain both fast response and high sampling accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses errors in digital signals by reducing the time required to charge the capacitor in the filter circuit, ensuring accurate AD conversion and minimizing phase delays in high-speed rotating applications.
Implementation Method 1
a filter circuit including a first capacitor C1 and reducing a predetermined frequency component of an analog signal
Implementation Method 2
a sample-and-hold circuit including a second capacitor C2 and sampling and holding the analog signal that has passed through the filter circuit
Implementation Method 3
a voltage application circuit applying a predetermined voltage to the second capacitor C2; a control unit applying the predetermined voltage to the second capacitor C2 through the voltage application circuit, thereby charging the second capacitor
Data Source
AI summary
A signal processing device and a control method therefor comprise: a filter circuit including a first capacitor and reducing a predetermined frequency component of an analog signal; a sample-and-hold circuit including a second capacitor and sampling and holding the analog signal that has passed through the filter circuit; and an AD conversion circuit converting an output signal from the sample-and-hold circuit into a digital signal, and a predetermined voltage is applied to the second capacitor, thereby charging the second capacitor, and the sample-and-hold circuit is then caused to sample the analog signal that has passed through the filter circuit. This suppresses the time required to charge the first capacitor and reduces errors in digital signals.