Sample-and-Hold Readout Circuit for Faster Ramp ADC Row Timing
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Solution Overview
Problem
Existing optical array sense and readout electronics require a large chip area, are prone to mismatch between sample and hold capacitors, and consume more power due to additional electronics needed for pipelining.
Innovation Solution
A sample and hold circuit that operates in three phases: hold, tracking, and sample, using a Field Effect Transistor based source follower with zero threshold voltage, which reduces the row time by pipelining the counting period with other pixel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipelining is implemented to reduce row time, then conversion speed is improved, but chip area and power consumption increase due to additional electronics
Solution Approach 1:
The patent merges the sample and hold capacitors into a single shared capacitor that is reused across multiple pixel rows. Instead of having separate capacitors for each row as in traditional pipelined architectures, this single capacitor is time-multiplexed to serve multiple rows sequentially, thereby eliminating the need for additional capacitor arrays while maintaining pipelining benefits.
Solution Approach 2:
The single sample and hold capacitor performs multiple functions by being shared across different pixel rows and different operational phases. It serves as both the sample capacitor for current row and the hold capacitor for previous rows, and can be dynamically reconfigured through switching networks to adapt to different readout requirements, thus replacing what would traditionally require multiple dedicated capacitors.
2Productivity
If pipelining is implemented to reduce row time, then conversion speed is improved, but power consumption increases due to additional electronics
Solution Approach 1:
The patent combines multiple capacitor functions into a single physical capacitor, thereby eliminating the power consumption associated with charging and discharging multiple separate capacitors. The single capacitor is time-multiplexed across different rows and phases, reducing overall dynamic power consumption while maintaining the pipelined conversion speed benefits.
3Measurement precision
If separate sample and hold capacitors are used for each pixel row, then conversion accuracy is improved, but mismatch between capacitors occurs
Solution Approach 1:
The patent uses a single shared capacitor for all pixel rows instead of separate capacitors for each row. This eliminates the capacitor-to-capacitor mismatch problem that plagues multi-capacitor designs, as there is only one capacitor whose characteristics remain consistent across all conversions. The single capacitor is time-multiplexed to serve multiple rows sequentially.
Solution Approach 2:
By using a single capacitor throughout the entire readout process, the patent ensures homogeneous capacitor characteristics across all pixel conversions. There is no variation between capacitors since there is only one capacitor, thereby eliminating the mismatch issues that arise from manufacturing tolerances and process variations in multi-capacitor designs.
4Reliability
If traditional sample and hold circuitry is used, then capacitor mismatch is eliminated, but additional electronics are required
Solution Approach 1:
The patent merges multiple capacitor functions into a single capacitor, thereby simplifying the overall circuit architecture. Instead of requiring multiple capacitors with precise matching, the design uses one capacitor with time-multiplexed access, reducing component count and interconnection complexity while achieving the same or better performance through the elimination of mismatch issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the row time, minimizes power consumption, and eliminates mismatches between capacitors, enabling faster frame rates and more efficient optical array readout.
Implementation Method 1
using a Field Effect Transistor based source follower with zero threshold voltage
Implementation Method 2
transfers the value of a charged sample and hold capacitor by using the capacitor voltage
Data Source
AI summary
A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.