Sample-and-Hold Current Sense Amplifier for Mismatch Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in developing low power circuits with reduced operating voltage and current consumption, while maintaining fast access speed for memory devices, particularly due to mismatch issues in sense amplifier circuits used in memory arrays.
Innovation Solution
A novel sense amplifier circuit employing sample-and-hold circuits to reduce mismatch by sampling and holding both cell and reference currents, allowing for accurate comparison and output signal generation, thereby eliminating traditional current mirror-induced mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If current mirrors are used in sense amplifier circuits, then circuit operation is simplified, but mismatch errors increase
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitors with reference currents before the sensing operation. The reference current is stored on capacitors in a first phase, then used in a second phase without requiring current mirrors during the actual sensing, thereby eliminating mismatch errors while maintaining circuit simplicity.
2Use of energy by moving object
If operating voltage and current are reduced for low power consumption, then power consumption decreases, but access speed becomes slower
Solution Approach 1:
The patent employs periodic action through multi-phase operation: a first phase for pre-charging capacitors with reference currents, and a second phase for sensing. This periodic structure allows the circuit to operate efficiently at low voltages and currents while maintaining fast access speeds by concentrating the high-speed operation in the sensing phase.
3Area of moving object
If integration density is increased by shrinking process node, then integration density improves, but operating voltage and current must be reduced
Solution Approach 1:
The patent applies parameter changes by transitioning from continuous current mirroring to discrete phased operation with capacitive storage. This allows the circuit to adapt to lower operating voltages and currents required by shrunk process nodes while maintaining sensing accuracy through the pre-charged capacitor approach.
Data Source
AI summary
A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.