Sample-and-Hold Circuit Shielding for Low Distortion ADC Sampling
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Solution Overview
Problem
Existing sample and hold (S/H) circuits suffer from distortion due to parasitic capacitance effects, particularly drain-to-source capacitance (CDS), which degrades accuracy in high-speed applications and increases power consumption when attempting to minimize these effects.
Innovation Solution
The implementation of a S/H circuit design that employs at least two transistors in series between the input and sampled nodes, with a switch coupling the node to ground during the sample period to shield the sampled node from parasitic currents, thereby maintaining a constant voltage and reducing distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional S/H circuit designs are used, then the circuit structure is simple, but distortion occurs due to parasitic capacitance effects degrading accuracy
Solution Approach 1:
The patent introduces an intermediate shielding node between the input and sampled nodes, coupled to a fixed voltage through a switch. This intermediary structure acts as a barrier that blocks parasitic capacitance coupling paths, preventing distortion from propagating to the sampled node while maintaining sampling accuracy.
Solution Approach 2:
The patent divides the traditional single-transistor S/H circuit into multiple segmented transistor stages with intermediate shielding nodes. By segmenting the circuit and isolating parasitic elements in separate stages, the distortion affecting the sampled node is minimized while preserving the core sampling function.
2Measurement precision
If conventional S/H circuits are used, then power consumption is lower, but distortion degrades accuracy in high-speed applications
Solution Approach 1:
The intermediate shielding node with fixed voltage coupling acts as a mediator that enables high-speed operation by blocking parasitic feedback paths. This allows the circuit to operate at higher speeds without the distortion that would normally degrade accuracy in high-speed applications.
3Measurement precision
If shielding techniques are applied to reduce parasitic effects, then distortion is reduced, but power consumption increases
Solution Approach 1:
The switch coupling the shielding node to fixed voltage operates periodically, switching between connected and disconnected states. During the disconnected state, the shielding node maintains its voltage without active driving, significantly reducing power consumption while still providing distortion reduction during the connected state.
Solution Approach 2:
The patent applies shielding selectively at critical nodes where parasitic capacitance has the most impact, rather than uniformly across the entire circuit. This localized approach reduces distortion where it matters most while minimizing the overall power consumption increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces distortion in S/H circuits, allowing for accurate signal sampling and holding without significant power consumption increases, making it suitable for advanced node and high-precision analog circuits, including those in fin field effect transistor (FINFET) processing.
Implementation Method 1
Existing sample and hold (S/H) circuits suffer from distortion due to parasitic capacitance effects, particularly drain-to-source capacitance (CDS)
Data Source
AI summary
A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.