Sample-and-Hold Varactor Correction for Capacitor Nonlinearity
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Solution Overview
Problem
Conventional sample-and-hold circuits suffer from nonlinear capacitance, leading to distorted sampled signals due to nonlinear current draw, which limits Spurious-Free Dynamic Range (SFDR) performance in analog-to-digital converter (ADC) applications.
Innovation Solution
A correction network comprising varactor cells, actuation circuits, and a boost circuit is introduced to counteract nonlinear current draw by providing control signals and reference voltages, coupled with a sampling switch and capacitor, to linearize the sampling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a linear sampling capacitor is used in a sample-and-hold circuit, then the circuit structure is simple, but nonlinear capacitance causes signal distortion and limits SFDR performance
Solution Approach 1:
The correction network is divided into multiple varactor cells arranged in rows and columns, with each cell independently controllable through actuation circuits. This segmentation allows precise control of capacitance values to cancel nonlinear effects while maintaining manageable circuit complexity
Solution Approach 2:
The invention changes the capacitance parameter dynamically by applying control signals to varactor cells, which vary their capacitance values based on the instantaneous voltage across the sampling capacitor. This parameter modulation cancels the nonlinear current draw and eliminates signal distortion
2Manufacturing precision
If conventional correction methods using multiple ADCs and differentiators are employed, then signal distortion is reduced, but power consumption and circuit area increase significantly
Solution Approach 1:
The invention merges the correction function directly into the sample-and-hold circuit by integrating varactor cells with the sampling capacitor. This combined structure eliminates the need for separate correction circuits like multiple ADCs and differentiators, reducing both power consumption and circuit area while maintaining signal accuracy
Solution Approach 2:
The varactor cells automatically adjust their capacitance based on the voltage across the sampling capacitor, creating a self-correcting mechanism that eliminates nonlinear distortion without requiring external correction circuits or additional power-consuming components
3Manufacturing precision
If conventional correction circuits are used, then capacitor nonlinearity is corrected, but circuit area consumption increases
Solution Approach 1:
The varactor cells are nested within the sample-and-hold circuit structure, with each varactor cell integrated alongside the sampling capacitor. This nested arrangement allows the correction function to be embedded within the existing circuit footprint, minimizing additional area consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces nonlinear current draw, enhancing SFDR performance by up to 13 dB in ADC applications without increasing circuit area or power consumption.
Implementation Method 1
A correction network having at least one row of varactor cells, wherein each varactor cell is coupled to the sampling node, and wherein each varactor cell in the row receives a reference voltage, and wherein each varactor cell receives at least one of a plurality of control signals
Data Source
AI summary
A sample-and-hold (S/H) circuit is provided. The S/H circuit generally comprises a sampling switch, a sampling capacitor, and a correction network. The sampling switch that receives an analog input signal is actuated and deactuated by a timing signal. The sampling capacitor is coupled to the sampling switch at a sampling node so as to receive the analog input signal when the sampling switch is actuated and to store a voltage of the analog input signal when the sampling switch is deactuated. The correction network has at least one row of varactor cells such that each varactor cell is coupled to the sampling node and wherein each varactor cell in the row receives a reference voltage. Additionally, each varactor cell receives at least one of a plurality of control signals.


