Sample Rate Conversion Using Parallel Modulus Accumulator Control
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Solution Overview
Problem
Existing sample rate conversion techniques face challenges in efficiently handling high input/output sampling rates, particularly in the GHz range, due to difficulties in operating filters and modulus accumulators at such high frequencies, and require complex polyphase implementations that are memory-intensive and computationally inefficient.
Innovation Solution
The use of polynomial-based filters with a farrow structure and modulus accumulator for delta value generation, implemented using digital hardware logic, operating at a slower clock rate and utilizing parallel architectures with FIFO buffers to facilitate efficient sample rate conversion, allowing for parallel operations and reduced memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional sample rate conversion techniques are used at high sampling rates, then sample rate conversion can be performed, but the system becomes computationally inefficient and memory-intensive due to complex polyphase implementations
Solution Approach 1:
The patent divides the sample rate conversion process into separate interpolation and decimation stages, each handled by dedicated hardware modules. The interpolation module up-samples the input signal by inserting zeros and filtering, while the decimation module down-samples by selecting specific samples. This segmentation allows each module to operate independently at optimized clock rates rather than requiring the entire system to run at the high input sampling rate, reducing computational complexity and memory requirements.
2Measurement precision
If filters and modulus accumulators are operated at high sampling rates (GHz range), then accurate sample rate conversion can be achieved, but the operational difficulty and computational load increase significantly
Solution Approach 1:
The patent introduces an intermediate representation stage where the input signal is first up-sampled to a higher rate using a zero-insertion filter, then processed through the conversion modules at this intermediate rate. This intermediary approach allows the system to maintain accuracy by working with properly sampled data while avoiding the need to operate all components directly at the highest possible frequency, thereby reducing operational difficulty.
Solution Approach 2:
The patent replaces traditional software-based filtering and accumulation operations with dedicated hardware logic circuits. The interpolation filter, decimation filter, and modulus accumulator are implemented as combinatorial logic and flip-flop based hardware modules that perform their functions in parallel clock cycles rather than sequential software iterations. This substitution eliminates the operational difficulties of running complex algorithms at GHz frequencies by using simplified hardware logic that can operate synchronously at high clock rates.
3Productivity
If polyphase implementations are used for sample rate conversion, then conversion can be performed, but memory usage increases significantly
Solution Approach 1:
The patent extracts and removes the zero-insertion steps from the traditional polyphase implementation, processing only the non-zero input samples through the filtering and decimation stages. By taking out the redundant zero-processing operations, the system reduces memory bandwidth requirements and storage needs while maintaining the same conversion functionality. This is achieved by having the hardware logic directly select and process valid input samples without requiring buffers to hold and process inserted zero values.
Data Source
AI summary
Systems, devices, and methods related to a sample rate converter (SRC) for implementing a rate conversion R are provided. The SRC receives input samples at an input rate Fin and outputs samples at an output rate Fout=Fin×R, where R is a fractional value greater than 1. The SRC includes a plurality of filters to process the received input samples and a multiplier-adder block to generate the output samples based on respective delta values and outputs of the plurality of filters. The SRC further includes a plurality of buffers to buffer samples between the plurality of filters and the multiplier-adder block based at least in part on N buffer read pointers, where N is an integer greater than 1. The SRC further includes resampler control circuitry to generate N delta values of the delta values and the N buffer read pointers in parallel based on R.