Sample Rate Conversion for Low-Power Digital Signal Time Shifting

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Solution Overview

Problem

In mobile communication systems, particularly for carrier aggregated LTE signals, digital delay blocks used to align in-phase and quadrature components of digital signals consume high power, which becomes a significant fraction of the transmitter's power budget, especially at higher bandwidths.

Innovation Solution

A sample rate converter is used to shift digital signals in time by modifying the time interval between sample times, allowing for time alignment without the need for additional delay elements, thereby reducing power consumption and circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If digital filter elements (first order all-pass filter) are used for time alignment of I and Q components, then time alignment precision is improved, but power consumption increases significantly

Engineering Contradiction:
Improvetime alignment precisionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent combines the time alignment function with the existing sample rate conversion process. The sample rate converter is modified to include a time shift capability, merging two functions (sample rate conversion and time alignment) into a single processing block, thereby eliminating the need for separate high-power digital filters

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The sample rate converter is designed to perform multiple functions: it converts sample rates and simultaneously provides time shifting capability for aligning I and Q components. This multi-functional approach replaces the dedicated digital filter elements with a versatile processing block that achieves the same time alignment goal with lower power consumption

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If digital filter elements are used for time alignment, then time alignment capability is improved, but device complexity increases

Engineering Contradiction:
Improvetime alignment capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the time alignment function with the sample rate conversion block, reducing the total number of separate circuit elements. Instead of having distinct digital filter components for time alignment, the functionality is integrated into the existing sample rate converter structure

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The sample rate converter is enhanced to provide both sample rate conversion and time shifting capabilities in a single processing unit. This multi-functional design reduces device complexity by eliminating the need for separate dedicated time alignment circuits

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If sample rate conversion is used for time shifting, then power consumption is reduced, but processing complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent performs time shifting as a preliminary action within the sample rate conversion process itself, rather than as a subsequent separate operation. By incorporating the time shift calculation into the sample rate conversion logic, the processing complexity is managed within an already-complex block rather than adding to it

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11575364B2Apparatuses and methods for shifting a digital signal by a shift time to provide a shifted signal
Publication Date: 2023.02.07 APPLE INC
  • US11575364B2 patent drawing
  • US11575364B2 patent drawing
  • US11575364B2 patent drawing

AI summary

An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.