Sampled Accumulation Jitter Attenuation
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Solution Overview
Problem
In synchronous communications networks, existing systems face challenges in efficiently managing clock variations and data rate fluctuations, leading to data loss and instability due to the ineffective filtering of low-frequency wander components and inconsistent buffer-fill information processing across multiple channels.
Innovation Solution
A sampled accumulation method is employed, where buffer-fill information from multiple tributaries is averaged and updated at a reduced rate, allowing for stable rate recovery and accurate stuff bit opportunity calculation, thereby regulating the data mapping into Synchronous Payload Envelopes (SPEs) without the need for parallel hardware sets for each channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If buffer-fill information is processed at full system clock rate for each channel, then measurement precision and reliability are improved, but device complexity and hardware requirements increase
Solution Approach 1:
The patent implements periodic sampling of buffer-fill information at a reduced rate (e.g., every 4th or 8th clock cycle) rather than processing every clock cycle. This periodic sampling maintains sufficient measurement precision for jitter attenuation while significantly reducing the hardware complexity and processing burden, directly resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The patent combines multiple channels of buffer-fill information into a single integrated filter structure that processes aggregated data from multiple tributaries. By merging the processing of multiple channels through a shared filter resource, the system achieves comprehensive monitoring without requiring separate full-rate processing hardware for each channel, thus reducing overall device complexity while maintaining measurement accuracy
2Reliability
If parallel hardware sets are used for each channel, then processing speed and reliability are improved, but device complexity and cost increase
Solution Approach 1:
The patent designs a universal filter structure that can process buffer-fill information from multiple different channels and tributary types through a single integrated hardware unit. This multi-functional approach allows the same hardware to serve multiple channels sequentially, ensuring reliable data rate recovery without requiring separate dedicated hardware sets for each channel, thereby reducing device complexity while maintaining reliability
Solution Approach 2:
The patent implements dynamic timesharing of the filter block, where the filter resource is dynamically allocated to different channels in a time-division manner. The system can switch between processing different tributaries based on current needs, providing flexible and reliable processing for multiple channels without the static overhead of parallel hardware, thus achieving reliability with reduced complexity
3Device complexity
If sampling rate is reduced for hardware efficiency, then device complexity decreases, but measurement precision and stability may worsen
Solution Approach 1:
The patent performs preliminary accumulation and averaging of buffer-fill information over multiple sampling periods before final processing. By pre-aggregating data from multiple reduced-rate samples, the system ensures that the final measured value represents a stable and accurate average, preventing instability that might result from simple reduced-rate sampling. This preliminary action maintains data rate stability while allowing hardware-efficient reduced sampling
Solution Approach 2:
The patent implements feedback mechanisms where the filtered output is continuously monitored and used to adjust subsequent processing parameters. The feedback loop ensures that even with reduced sampling rates, the system can detect and correct deviations in data rate stability, maintaining compositional stability through active control while benefiting from the hardware efficiency of lower sampling rates
Data Source
AI summary
A system and method are provided for a sampled accumulation method that maps information into Synchronous Payload Envelopes (SPEs). The method buffers data from a plurality of tributaries, and sequentially stores buffer-fill information for each tributary in a first memory, at a rate of up to one tributary per system clock (Fsys) cycle. A stored accumulation of buffer-fill information for each tributary is updated at a sample rate frequency (Fsample), where Fsample≦Fsys. The stored accumulation of buffer-fill information is used to calculate stuff bit opportunities for each tributary. As a result, the rate of data being mapped into outgoing tributaries is regulated, and the outgoing mapped tributaries are combined in a SPE.