Sampled Analog Clock Distribution With Local Phase Synchronization
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Solution Overview
Problem
In large system-on-chip (SoC) devices, synchronizing the phases of multiple sampled analog circuits is challenging due to the difficulty in distributing a precisely aligned global clock signal, which consumes significant power and leads to inefficiencies in data transfer between circuits.
Innovation Solution
Each sampled analog circuit operates with a local phase clock triggered by a master clock, and a data transfer circuit manages data transfer between circuits to prevent temporal overlap, allowing for decentralized clock alignment and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a common master clock is distributed to all sampled analog circuits, then phase alignment is achieved, but power consumption increases significantly
Solution Approach 1:
The patent divides the centralized clock distribution system into multiple independent local phase clock generators, each circuit generating its own phase clocks locally based on a trigger signal. This segmentation eliminates the need for distributing a common master clock to all circuits, thereby significantly reducing power consumption while maintaining phase alignment through the trigger-based synchronization mechanism.
Solution Approach 2:
The patent introduces a trigger signal as an intermediary mechanism that coordinates the local phase clock generators without requiring direct distribution of the master clock. The trigger signal acts as a mediator that enables phase alignment between circuits while avoiding the high power consumption associated with distributing clock signals across the entire chip.
2Use of energy by moving object
If local phase clocks are used in each circuit, then power consumption is reduced, but phase alignment between circuits becomes difficult
Solution Approach 1:
The patent employs a trigger signal mechanism that provides feedback-based synchronization. Each local phase clock generator is triggered by a common trigger signal, ensuring that all circuits operate in synchronized phases. This feedback mechanism maintains phase alignment precision while allowing each circuit to generate its own clocks locally, thus reducing power consumption.
Solution Approach 2:
The trigger signal is distributed in advance to all local phase clock generators before the actual data transfer operations begin. This preliminary action ensures that all circuits are pre-synchronized and ready to operate in phase, eliminating the need for continuous clock distribution while maintaining alignment precision.
3Adaptability or versatility
If data transfer is managed between circuits with different phase clocks, then circuit independence is maintained, but temporal overlap may occur
Solution Approach 1:
The patent introduces a data transfer circuit as an intermediary component that manages data exchange between circuits with independent local phase clocks. This intermediary ensures that data transfers are coordinated and that temporal overlaps are prevented, thereby maintaining data transfer reliability while preserving circuit independence.
Solution Approach 2:
The data transfer circuit dynamically adjusts the timing of data transfers based on the phase relationships between different local clocks. By making the transfer timing dynamic rather than fixed, the system can adapt to different clock phases and prevent overlaps, ensuring reliable data transfer between independent circuits.
Data Source
AI summary
Sampled analog data are transferred between sampled analog circuits operating on respective local phase clocks which are triggered by a master clock. In response to a first (DATA READY) signal from an upstream sampled analog circuit, the sampled analog data are transferred from an upstream sampled analog circuit to a data transfer circuit. In response to a second (READY FOR DATA) signal from a downstream sampled analog circuit, the sampled data are transferred from the data transfer circuit to the downstream sampled analog circuit. The sampled data are delayed in the data transfer circuit for at least one master clock cycle when the second signal from the downstream sampled analog circuit is received before the first signal is received from the upstream sampled analog circuit.