Sampled CMOS Switch Architecture for Low-Voltage High-Speed Sampling
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Solution Overview
Problem
Existing electronic switch architectures face challenges in operating at low supply voltages, particularly in CMOS switches, where the sum of threshold voltages of PMOS and NMOS devices exceeds the rail-to-rail signal voltage, requiring large switch areas and experiencing phase delays and signal-to-noise ratio degradation due to asynchronous sampling clocks.
Innovation Solution
The implementation of a sampled CMOS switch circuit using series-connected NMOS devices and DEPMOS devices in a 'T' configuration, with a feedback circuit including a high-voltage NMOS device and current source, allows for reduced threshold voltage and protected gate oxide insulation, enabling operation across a wide input signal range with reduced switch area and minimizing phase delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional CMOS switch architecture is used, then the switch can operate with standard threshold voltages, but the sum of threshold voltages exceeds the supply voltage range requiring large switch area
Solution Approach 1:
The patent changes the threshold voltage parameter of the MOS devices by using extended drain structures that modify the electric field distribution, effectively reducing the threshold voltage to enable operation with lower supply voltages while maintaining adequate switch area
Solution Approach 2:
The patent introduces extended drain regions that protrude into the channel region, creating a three-dimensional electric field structure that reduces the effective threshold voltage without increasing the planar switch area
2Reliability
If asynchronous sampling clock is used, then the sampling can be independent of internal ADC clock, but phase delay occurs resulting in sampling error and degraded signal-to-noise ratio
Solution Approach 1:
The patent implements a feedback mechanism where the sampling clock is synchronized to the internal ADC clock, eliminating phase delay and sampling errors while maintaining the ability to operate with external sampling signals through controlled clock generation
3Adaptability or versatility
If low voltage DEPMOS devices are used, then the threshold voltage is reduced enabling low supply voltage operation, but gate oxide reliability is compromised
Solution Approach 1:
The patent provides beforehand protection for the gate oxide by introducing a protective structure that prevents high electric field stress from damaging the gate oxide, enabling the use of low threshold voltage DEPMOS devices without compromising reliability
Data Source
AI summary
A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a âTâ configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.