Sampled CMOS Switch Topology for Low-Voltage Sampling
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Solution Overview
Problem
CMOS switches face challenges in operating at low supply voltages, requiring large switch areas and experiencing phase delays and signal-to-noise ratio degradation due to asynchronous sampling clocks, which lead to kick-back issues and increased switch area requirements.
Innovation Solution
The implementation of a sampled CMOS switch circuit using NMOS and DEPMOS devices in series with a feedback circuit, including a pair of extended drain MOS devices in a 'T' configuration, activated by an inverted sample signal, and a third NMOS device with a current source to protect gate oxide insulation and manage threshold voltages, allowing for efficient low-voltage operation and reduced switch area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a CMOS switch uses standard threshold voltage devices, then the switch can operate at higher supply voltages, but the switch area becomes excessively large when operating at low supply voltages
Solution Approach 1:
The patent divides the single switch structure into two parallel switches with different threshold voltages. One switch uses a standard threshold voltage device while the other uses a low threshold voltage device. This segmentation allows the circuit to handle different voltage ranges efficiently, enabling low-voltage operation without requiring excessive switch area.
Solution Approach 2:
The patent applies different threshold voltage characteristics to different parts of the switch circuit. Specifically, it uses a low threshold voltage switch for the low-voltage path and a standard threshold voltage switch for the high-voltage path. This local differentiation optimizes the switch area for low-voltage operation while maintaining high-voltage capability when needed.
2Ease of operation
If a sampling clock is used to operate the switch, then the switch can be controlled for sampling operations, but phase delays and signal-to-noise ratio degradation occur when the sampling clock is asynchronous to the ADC clock
Solution Approach 1:
The patent introduces a feedback mechanism that monitors the relationship between the sampling clock and ADC clock. When phase delay is detected, the system adjusts the sampling timing or generates correction signals to compensate for the asynchrony. This feedback loop eliminates kick-back effects and prevents sampling errors caused by clock mismatch.
Solution Approach 2:
The patent performs preliminary synchronization of the sampling clock with the ADC clock before the actual sampling operation. By pre-aligning the clock phases and adjusting timing relationships in advance, the system prevents phase delays and kick-back effects from occurring during the critical sampling window, thereby maintaining high sampling accuracy.
3Temperature
If a boost switch is used to extend the voltage range, then the switch can handle higher voltage differences, but the switch becomes unusable due to very large clock time periods or unavailable clock signals
Solution Approach 1:
The patent introduces an intermediate voltage buffer or level-shifting circuit between the low-voltage and high-voltage domains. This intermediary component allows the switch to handle voltage transitions without requiring extreme clock time periods. The buffer circuit mediates the voltage difference, enabling the switch to operate across a wide voltage range using standard clock frequencies.
Data Source
AI summary
A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a âTâ configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.