Sampled Comparator Auto-Zeroing With Dual Reference Band
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Solution Overview
Problem
Conventional offset cancellation techniques for comparators suffer from digital oscillation issues when nearing zero offset, which can lead to jitter in clock frequency or duty cycle, especially in applications requiring consistent threshold values.
Innovation Solution
The proposed solution involves a circuit and method that uses two auto-zeroing cycles with voltages VREF+VBAND and VREF−VBAND to time-multiplex the comparator, allowing the offset to be forced within a band around zero, thereby eliminating digital oscillation and maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital offset cancellation is used to achieve high offset accuracy, then measurement precision is improved, but digital oscillation occurs causing jitter in clock frequency
Solution Approach 1:
The patent applies periodic action by using two distinct auto-zeroing cycles with different reference voltages (VREF+VBAND and VREF-VBAND) to time-multiplex the comparator. This periodic switching between different reference levels prevents the comparator from dwelling at the sensitive zero-crossing point, thereby eliminating digital oscillation while maintaining offset accuracy within a defined band.
2Measurement precision
If storage capacitors are used to cancel offset, then accuracy is improved, but device area increases and charge leakage occurs
Solution Approach 1:
The patent extracts and eliminates the storage capacitor component from the offset cancellation mechanism. Instead of using capacitors to hold offset voltages, the invention employs a capacitor-less auto-zeroing technique that uses periodic switching between two reference voltages to force the offset within an acceptable band, thereby removing the source of charge leakage and reducing device area.
3Manufacturing precision
If device area is increased to reduce process variations, then manufacturing precision is improved, but parasitic capacitances increase reducing speed
Solution Approach 1:
The patent applies parameter changes by introducing a band of acceptable offset values (±VBAND) rather than requiring precise zero offset. This relaxation of the offset parameter allows the use of smaller devices with lower parasitic capacitances, thereby maintaining manufacturing precision through statistical process control while improving comparator speed and reducing power consumption.
Data Source
AI summary
A comparator compares an input voltage and a reference voltage and generates an output based on the comparison. The comparator may receive the input voltage in a normal mode of operation. Voltage band circuitry provides first and second test voltages to the comparator. The test voltages define a band around the reference voltage. An integrator adjusts an offset correction signal provided to the comparator based on outputs of the comparator that are generated using the test voltages. The output of the comparator that is generated using the first test voltage could be generated during a first auto-zeroing cycle. The output of the comparator that is generated using the second test voltage could be generated during a second auto-zeroing cycle. This technique helps to maintain the offset of the comparator with the band around the reference voltage.