Sampled Current-Integrating Decision Feedback Equalizer
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Solution Overview
Problem
Current decision feedback equalizers (DFE) with resistive summers face settling time degradation and increased power consumption as more feedback taps are added, and the use of current-integrating summers introduces additional signal loss due to frequency-dependent integrator loss, making it difficult to compensate high-loss channels effectively.
Innovation Solution
Implementing a DFE architecture with a sample-and-hold element and a current-integrating summer that samples and holds the input signal constant during integration, mitigating the effects of input transitions and reducing power consumption by eliminating settling time requirements, while minimizing additional losses through frequency-independent integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more feedback taps are added to compensate for multiple postcursors, then intersymbol interference compensation is improved, but capacitive loading at the summation node increases degrading settling time
Solution Approach 1:
The patent replaces the resistive loading mechanism with a current-integrating summation mechanism. Instead of using resistors to sum currents (which creates capacitive loading at the node), the invention uses current mirrors and integrating summers that accumulate current over time without creating voltage nodes subject to capacitive loading. This substitution of the summation mechanism eliminates the fundamental cause of settling time degradation while preserving the ability to add multiple feedback taps for ISI compensation.
2Loss of time
If load resistance is decreased to improve settling time, then settling time is improved, but higher current levels and thus higher power consumption are required
Solution Approach 1:
The invention substitutes the resistive voltage-summing approach with a current-integrating approach. The current-integrating summer accumulates current from multiple taps over the bit period without requiring low resistance loads, thereby avoiding the need to increase current levels and power consumption. The integration process naturally sums currents without creating the voltage node that would require low resistance for fast settling.
3Loss of time
If current-integrating summer is used to eliminate settling time requirements, then settling time requirements are eliminated, but additional signal loss is introduced due to frequency-dependent integrator loss
Solution Approach 1:
The patent introduces dynamic equalization by sampling the input signal at the optimal decision point and holding it constant during the integration period. This dynamic sampling and holding approach allows the system to capture the peak signal value and maintain it throughout integration, thereby compensating for the frequency-dependent loss that would otherwise attenuate higher frequency components. The dynamic nature of the sampling clock, synchronized to the data rate, ensures optimal signal capture.
Solution Approach 2:
The sample-and-hold circuit performs preliminary action by capturing and holding the input signal value before the integration process begins. This preliminary sampling at the optimal decision point ensures that the maximum signal value is captured and maintained during integration, preventing signal loss that would occur if integration began with a transitioning or decaying signal.
4Duration of action of stationary object
If integration continues during transitions from 1 to 0 or vice versa, then integration is continuous, but output voltage is lower than ideal case where input levels remain constant
Solution Approach 1:
The sample-and-hold circuit performs preliminary action by capturing the input signal value at the optimal decision point before integration begins. By holding this sampled value constant during the entire integration period, the system ensures that integration always occurs on a constant value rather than a transitioning signal. This preliminary sampling action prevents the accuracy degradation that would result from integrating during transitions.
Solution Approach 2:
The system employs periodic sampling synchronized to the data rate, where the input signal is sampled at regular intervals corresponding to bit boundaries. This periodic action ensures that sampling occurs at optimal points in the signal waveform, capturing peak values and maintaining them during integration. The periodic nature of the sampling clock, synchronized to the incoming data rate, ensures consistent and accurate signal capture across all bits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased number of taps without significant power penalty and reduces bit error rate by maintaining signal integrity, effectively compensating high-loss channels with improved signal-to-noise ratio.
Implementation Method 1
a current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node
Data Source
AI summary
A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.