Sampled PLL Loop Filter for Low-Noise Fractional-N Clocking
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Solution Overview
Problem
Existing methods and systems for voltage-controlled-oscillators (VCOs) in phase locked loops (PLLs) often introduce disturbances and handle them inefficiently, particularly in communication systems that rely on wireless and wired connections for RF signal processing.
Innovation Solution
A sampled loop filter in a PLL is implemented, comprising a phase frequency detector, a plurality of capacitors, and a frequency divider, which samples an output signal when the average charge provided to the capacitors is zero, using a fractional-N divider to provide a filtered output voltage for the VCOs and mitigate noise through non-overlapping switching times and sub-sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional loop filter is used in a PLL, then the circuit can operate continuously, but noise and spurs are introduced in the output signal
Solution Approach 1:
The patent implements a sampled loop filter that operates periodically rather than continuously. The filter samples the output signal at specific intervals determined by a sampling clock, processing only during active sampling phases and remaining inactive during idle phases. This periodic operation reduces noise and spurs by limiting when the filter actively modifies the signal, while still maintaining effective PLL operation through timely sampling of phase error corrections.
Solution Approach 2:
The patent extracts the filtering function from a continuous operation mode and isolates it to specific sampling moments. By taking out the active filtering action from continuous time and concentrating it into discrete sampling instants, the system achieves noise reduction while maintaining essential signal processing capabilities. The filter is effectively removed from the signal path during non-sampling periods.
2Measurement precision
If sampling is performed at reference frequency, then phase error detection is accurate, but reference spurs are generated in the output
Solution Approach 1:
The patent changes the sampling frequency parameter from the reference frequency to a sub-multiple of the reference frequency. The sampling clock is derived by dividing the reference clock by an integer factor, creating a lower sampling rate. This parameter change allows the system to maintain phase error detection accuracy at the lower sampling rate while avoiding the generation of reference spurs that would occur at the full reference frequency.
Solution Approach 2:
The patent introduces a frequency divider as an intermediary between the reference clock and the sampling clock. This intermediary component transforms the reference frequency into a sub-multiple frequency, mediating between the need for accurate phase error detection and the need to avoid reference spurs. The frequency divider enables the sampling process to occur at a reduced rate that eliminates spur generation while preserving detection accuracy.
3Adaptability or versatility
If fractional-N division is used, then frequency synthesis flexibility is improved, but phase error signal becomes distorted
Solution Approach 1:
The patent employs periodic sampling of the phase error signal at a rate that is synchronized with the fractional-N division cycle. By sampling at specific periodic intervals that align with the completion of division cycles, the system captures accurate phase error information without being affected by the intermediate distorted states that occur during fractional division transitions. This periodic sampling approach maintains signal integrity while benefiting from frequency synthesis flexibility.
Solution Approach 2:
The patent performs preliminary sampling of the phase error signal at a reduced rate before the distortion from fractional-N division fully manifests. By anticipating and capturing the phase error information at optimal moments in the division cycle, the system preserves signal integrity. The preliminary sampling action occurs before distortion can corrupt the signal, allowing accurate phase error detection to proceed despite the use of fractional-N division for frequency synthesis.
Data Source
AI summary
Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.