Sampled PLL Loop Filter for Fractional-N Spur Reduction
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Solution Overview
Problem
Existing methods and systems for voltage-controlled-oscillators (VCOs) in phase locked loops (PLLs) often introduce disturbances and handle them inefficiently, particularly in communication systems that rely on wireless and wired connections for RF signal processing.
Innovation Solution
A sampled loop filter in a PLL is implemented, comprising a phase frequency detector, a plurality of capacitors, and a frequency divider, with a fractional-N divider to generate clock signals and provide a filtered output voltage for VCOs, using non-overlapping switching times and sub-sampling to mitigate noise and spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional loop filter is used in a PLL, then the circuit is simple, but noise and spurs are introduced in the output signal
Solution Approach 1:
The loop filter is segmented into multiple capacitor banks (first capacitor bank, second capacitor bank, third capacitor bank) that are selectively connected to different nodes (node A, node B, node C) based on the fractional divider state. This segmentation allows the filter to process different signal components at different stages, reducing noise and spurs while maintaining manageable circuit complexity through modular organization.
Solution Approach 2:
Multiple intermediate nodes (node A, node B, node C) are introduced between the phase frequency detector and the VCO. These intermediary nodes serve as staging points where charge is accumulated and redistributed, allowing the filter to mitigate noise and spurs progressively as the signal passes through each stage, rather than requiring a single complex filtering operation.
2Adaptability or versatility
If fractional-N division is used to achieve multi-frequency operation, then frequency versatility is improved, but reference spurs and noise are generated
Solution Approach 1:
The loop filter operates periodically, cycling through different capacitor connections to nodes A, B, and C in synchronization with the fractional divider's periodic switching between integer division ratios. This periodic action allows the filter to systematically address and reduce reference spurs generated during frequency switching, while maintaining the ability to operate at multiple frequencies through the fractional-N division mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces noise and spurs in the output signal, ensuring stable frequency generation and improved signal processing efficiency in communication systems, particularly in multi-standard and multi-frequency environments.
Implementation Method 1
a sampled loop filter comprising a plurality of capacitors and at least one switch
Implementation Method 2
the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero
Data Source
AI summary
Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.