Multi-Standard Sampler Circuit With Amplification for Faster Clock-to-Q
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Solution Overview
Problem
Existing sampler circuits based on regenerative latches fail to meet specified clock-to-q timing at higher data rates, leading to functional failures due to increased data rates.
Innovation Solution
A new sampler circuit design that incorporates a dedicated amplification phase, reducing the integration phase duration of the latch circuit and providing a larger voltage differential before the regenerative phase, thereby improving clock-to-q timing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rate is increased to improve productivity, then communication speed improves, but clock-to-q timing fails leading to functional failures
Solution Approach 1:
The sampling process is segmented into distinct phases: an amplification phase that operates independently before the regenerative latch phase. This segmentation allows the amplification phase to prepare sufficient voltage differential in advance, enabling the regenerative latch to activate sooner and meet timing requirements at higher data rates without functional failures
Solution Approach 2:
The amplification phase performs preliminary action by establishing a larger voltage differential before the regenerative latch phase begins. This preliminary preparation reduces the time required for the regenerative latch to switch, thereby improving clock-to-q timing and preventing functional failures at high data rates
2Reliability
If regenerative latch phase duration is extended to improve reliability, then sampling accuracy improves, but clock-to-q timing increases reducing productivity
Solution Approach 1:
The amplification phase performs preliminary action by establishing a larger voltage differential before the regenerative latch phase begins. This preliminary preparation ensures that when the regenerative latch activates, it has sufficient voltage headroom to switch quickly and reliably, thereby maintaining sampling accuracy while reducing the duration of the regenerative phase and improving clock-to-q timing
Data Source
AI summary
A sampler circuit for use with a serial communication bus includes an amplifier circuit, an isolation circuit, and a latch circuit. During a first phase, the amplifier circuit amplifies a voltage difference between a first input signal and a second input signal received via the communication bus to generate a voltage difference on output nodes of the latch circuit. During an integration phase, the latch circuit increases the voltage difference on the output nodes. During a regeneration phase, the isolation circuit isolates the amplifier circuit from the latch circuit, which generates full-rail signals based on a voltage difference between the output nodes.