AC-Coupled Sampler Circuit for Low-Noise SerDes Offset Correction
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Solution Overview
Problem
High-speed data links, such as those used in FPD-Link applications, face challenges in sensitivity and signal-to-noise ratio (SNR) due to the noise introduced by the differential input pairs used for offset voltage application in sampler circuits.
Innovation Solution
The proposed sampler circuit applies an offset voltage to the input signal without using a second differential input pair, instead AC-coupling the offset voltage to the input signal differential pair, which provides a high impedance input and reduces noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a second differential input pair is used to apply offset voltage, then the offset voltage can be applied to the input signal, but noise is introduced and sensitivity is reduced
Solution Approach 1:
The patent extracts the offset voltage application function from the traditional second differential input pair and implements it through a separate offset voltage source coupled to the gate of the first transistor. This separation removes the noise-generating differential pair while preserving the offset adjustment capability, thereby improving sensitivity without introducing excess noise.
Solution Approach 2:
The patent introduces an intermediary offset voltage source that couples to the gate of the first transistor through a capacitor. This intermediary structure allows offset voltage to be applied without requiring a second differential input pair, thus eliminating the noise source while maintaining the offset adjustment function needed for sensitivity optimization.
2Adaptability or versatility
If a second differential input pair is used for offset voltage application, then offset adjustment is possible, but the circuit complexity increases
Solution Approach 1:
The patent extracts the offset voltage application function from the second differential input pair and implements it through a simpler offset voltage source coupled to the gate of the first transistor. This reduction in circuit elements maintains offset adjustment capability while significantly reducing circuit complexity.
3Productivity
If high speed operation is implemented, then data transmission rate increases, but sensitivity and SNR deteriorate
Solution Approach 1:
By removing the noise-generating second differential input pair while preserving offset adjustment capability through the simplified offset voltage source, the patent enables high-speed operation with improved SNR. The elimination of the noisy differential pair structure allows faster operation without the penalty of reduced sensitivity.
Data Source
AI summary
In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.