Multi-Stage Sampler Circuit for Metastability-Free PLL Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital phase detectors in PLLs are susceptible to meta-stability issues due to asynchronous sampling and reference clocks, leading to hysteresis and dead-zone/dead-time problems, which can cause the DPLL to freeze when sampling near zero-crossing of the phase difference.
Innovation Solution
A sampler circuit with series-connected sampler cells, each comprising two parallel branches of clocked inverters, where each inverter operates as a Sample & Hold circuit with gain, using the input capacitance of the next inverter to store logic levels, and is clocked with opposite phases of the sampling clock, eliminating meta-stability by ensuring clear logic-0 or logic-1 resolution without regenerative feedback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous sampling is used between sampling clock and reference clock, then the DPLL can operate with flexible clock frequencies, but meta-stability problems occur leading to hysteresis and dead-zone issues
Solution Approach 1:
The sampling circuit is divided into multiple sequential sampler stages, each operating at a different clock frequency. The first stage samples at the higher reference clock frequency, while subsequent stages sample at progressively lower frequencies derived from the sampling clock. This segmentation allows the system to maintain flexibility in clock frequency selection while eliminating meta-stability by ensuring that each stage operates with properly synchronized clocks rather than asynchronous clocks.
2Power
If regenerative gain is used in digital phase detectors, then signal amplification is achieved, but hysteresis and dead-zone/dead-time problems occur
Solution Approach 1:
The invention extracts and removes the regenerative feedback mechanism from the sampling circuit. Instead of using traditional digital phase detectors with regenerative gain that cause hysteresis and dead-zone problems, the circuit uses simple sampling stages followed by a detector that processes the sampled signals without regenerative amplification. This extraction of the problematic regenerative element eliminates hysteresis and dead-zone issues while maintaining the ability to detect phase differences through the sampled signal transitions.
3Measurement precision
If traditional digital phase detectors are used, then phase difference measurement is achieved, but the detectors are not sensitive and suffer from dead-time
Solution Approach 1:
The invention performs preliminary sampling of the reference clock signal at multiple frequency stages before the final detection step. By pre-sampling the signal at higher frequencies and capturing the transitions in advance, the detector can then operate at lower frequencies with high sensitivity. This preliminary action preserves phase difference measurement accuracy while eliminating dead-time and enhancing detection sensitivity, as the critical sampling occurs before the slower detection stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively eliminates meta-stability concerns, allowing for accurate detection of state transitions in digital PLLs, reducing power consumption, and preventing DPLL freezing, while maintaining high sensitivity and avoiding hysteresis and dead-zone issues.
Implementation Method 1
each clocked inverter operates as a Sample & Hold circuit with gain, wherein the holding capacitor is the input capacitance of the next inverter
Data Source
AI summary
A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous stage, and is clocked at half the sampling frequency of the previous stage. Each sampler cell comprises two parallel branches of series-connected clocked inverters. A clocked inverter is operative to invert an applied signal during one phase of an applied sampling clock, and to render a high impedance output during the other sampling clock phase. Successive clocked inverters are clocked with opposite (i.e., positive/negative) versions of the sampling clock. The detector circuit examines the outputs of the last stage of sampler cells, and may for example comprise an OR function to detect a state transition in an applied input signal. The sampler circuit exhibits immunity to metastability and low power consumption.