Data Sampler Equalization Using Variable Negative Resistance

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Solution Overview

Problem

Conventional sampler circuits face challenges in maintaining input sensitivity due to inter-symbol interference and channel attenuation, which are exacerbated by the RC time constant, leading to decreased performance at higher clock frequencies.

Innovation Solution

The implementation of a data sampler circuit with a transconductance amplifier, latch circuit, current-to-voltage converter, and a variable gain negative resistance equalizing circuit that provides tunable equalization during both sampling and latching modes, improving input sensitivity by compensating for high-frequency gain responses and adjusting gain based on pulse width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional sampler circuits are used, then the circuit structure is simple, but input sensitivity decreases due to inter-symbol interference and channel attenuation

Engineering Contradiction:

Improveinput sensitivityVSAvoidcircuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A negative resistance equalizing circuit is introduced as an intermediary component between the data input and the sampler circuit. This equalizing circuit compensates for inter-symbol interference and channel attenuation by providing negative resistance that counteracts the harmful effects of channel loss, thereby maintaining input sensitivity without requiring complete redesign of the sampler structure

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The sampler circuit is designed to perform multiple functions: sampling, equalization, and latching. The equalizing circuit is integrated into the sampler structure, allowing it to simultaneously compensate for channel effects while performing the primary sampling function, reducing the need for separate dedicated equalization stages

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If clock frequency is increased, then productivity improves, but input sensitivity decreases due to RC time constant constraints

Engineering Contradiction:

Improveclock frequencyVSAvoidinput sensitivity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The negative resistance equalizing circuit dynamically adjusts its parameters to compensate for the effects of higher clock frequencies. By changing the equalization parameters in response to frequency variations, the circuit maintains input sensitivity even as productivity increases through higher clock rates

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The equalizing circuit is designed with dynamic characteristics that allow it to adapt to varying operating conditions. The circuit responds to changes in clock frequency and signal characteristics by adjusting its equalization effect, maintaining optimal performance across different productivity levels

Inventive Principle:

Principle #15Dynamics

3Reliability

If equalization is applied, then input sensitivity is improved, but device complexity increases

Engineering Contradiction:

Improveinput sensitivityVSAvoidcircuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The equalization function is merged with the sampling circuit structure. The negative resistance equalizing circuit is integrated directly into the sampler, combining what would traditionally be separate equalization and sampling stages into a unified circuit architecture, thereby reducing overall system complexity

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances input sensitivity and signal quality by effectively addressing inter-symbol interference and channel attenuation, maintaining consistent signal amplitudes across varying pulse widths and frequencies.

Implementation Method 1

a negative resistance circuit coupled to the output of the transconductance amplifier

Methodology Applied

Scientific EffectNegative resistance:

Implementation Method 2

a transconductance amplifier having an input and an output

Methodology Applied

Scientific EffectTransconductance:

Implementation Method 3

a current-to-voltage converter having an input coupled to the output of the transconductance amplifier, and an output for providing a feedback signal to the latch circuit

Methodology Applied

Scientific EffectFeedback: Feedback

Data Source

PatentUS9621136B1Data sampler circuit with equalization function and method for sampling data

Publication Date: 2017.04.11 NXP USA INC

AI summary

A data sampler circuit comprises a transconductance amplifier, a latch circuit, a current-to-voltage converter, and a negative resistance circuit. The transconductance amplifier has an input and an output. The latch circuit is coupled to the output of the transconductance amplifier. The current-to-voltage converter has an input coupled to the output of the transconductance amplifier, and an output for providing a feedback signal to the latch circuit. The negative resistance circuit is coupled to the output of the transconductance amplifier and provides equalization during both a sampling mode and a data latching mode. In one embodiment, the negative resistance circuit comprises a pair of cross-coupled transistors. A gain of the negative resistance circuit can be adjusted based on a pulse width of an input signal.