Non-Interleaving Sampling Amplifier Circuit for Low-Noise CCD Signals
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Solution Overview
Problem
Current semiconductor devices for signal sampling and amplification in integrated circuits face challenges with noise and require specific clock signals, leading to inefficiencies and increased input sampling capacitance, particularly in low noise applications like CCD signal amplification.
Innovation Solution
A non-interleaving circuit architecture that includes operational amplifiers, input and output capacitors, sampling and holding switches, and combined switches, allowing for signal sampling and amplification in a single clock cycle without the need for specific clock signals, and performs operational amplifier offset calibration, reducing input sampling capacitance to 4-8 pF.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a non-interleaving circuit architecture is used for signal sampling and amplification, then noise is reduced and input sampling capacitance is reduced to 4-8 pF, but the circuit requires operational amplifier offset calibration and cannot process multiple signals simultaneously
Solution Approach 1:
The circuit is divided into separate functional blocks: sampling switches (first and second), holding capacitors (first and second), and operational amplifiers (first and second). Each block performs a specific function independently, allowing the circuit to reduce noise through dedicated low-noise amplification paths while maintaining manageable complexity through modular design.
Solution Approach 2:
The operational amplifiers perform multiple functions: they amplify the sampled signals from the holding capacitors and also undergo offset calibration during the same clock cycle. This multi-functionality reduces the need for separate calibration circuits while maintaining low noise performance.
2Productivity
If signal sampling and amplification is performed in a single clock cycle, then processing speed is improved and time is reduced, but the circuit cannot perform offset calibration separately
Solution Approach 1:
The circuit uses periodic clock signals to control the sampling and amplification process. During specific phases of the clock cycle, the operational amplifiers perform offset calibration, while during other phases, they amplify the sampled signals. This periodic alternation allows both calibration and high-speed processing within the same clock cycle framework.
Solution Approach 2:
The operational amplifiers perform offset calibration in advance during the first clock cycle before signal amplification begins in subsequent cycles. This preliminary calibration ensures measurement precision is established beforehand, allowing high-speed processing without compromising accuracy in later operations.
3Measurement precision
If specific clock signals are required for sampling and amplification, then signal timing is controlled precisely, but the circuit loses efficiency and requires specific clock signals
Solution Approach 1:
The circuit uses dynamic clock signal generation where the sampling and amplification clock signals are derived from a single input clock signal through internal logic. This dynamic approach maintains precise timing control through phase relationships while improving efficiency by eliminating the need for multiple external clock signals, allowing the circuit to adapt its timing internally.
Data Source
AI summary
A circuit includes: an operational amplifier, having a first input terminal, a second input terminal, a first output terminal and a second output terminal; a plurality of sampling switches, having a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch; a plurality of holding switches, having a first holding switch and a second holding switch, the first holding switch coupled to the first node and the first output terminal, the second holding switch coupled to the second node and the second output terminal; and a plurality of combined switches, having a first combined switch and a second combined switch, the first combined switch coupled to the first input terminal, the second combined switch coupled to the second input terminal.