Memory Data Sampling Circuit With Offset Compensation for Low Kickback Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The DQ data sampling circuit in LPDDR4/5 memory experiences significant kickback noise due to the sampling circuit's offset voltage, which is exacerbated by the offset compensation circuit, and requires improved speed and reduced noise performance.
Innovation Solution
The data sampling circuit incorporates a second sampling circuit and offset compensation circuit connected to transistors, utilizing N-type transistors with minimized threshold voltage and substrate bias effect, along with a reset circuit to enhance speed and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an offset compensation circuit is added to compensate the sampling circuit, then the offset voltage is reduced, but the kickback noise increases
Solution Approach 1:
The sampling circuit is divided into two separate sampling circuits: a first sampling circuit for sampling input data and a second sampling circuit for sampling reference voltage. This segmentation isolates the offset compensation function to the second sampling circuit, preventing kickback noise from affecting the first sampling circuit while still achieving offset compensation.
Solution Approach 2:
A dedicated offset compensation circuit is introduced as an intermediary component that specifically compensates the second sampling circuit's offset voltage. This intermediary structure allows offset compensation to be applied selectively without directly impacting the first sampling circuit's noise performance.
2Speed
If the operating speed of the DQ data sampling circuit is increased to match faster input signals, then the sampling speed is improved, but the kickback noise becomes more significant
Solution Approach 1:
By separating the sampling function into two independent sampling circuits operating at different speeds, the first sampling circuit can be optimized for high-speed data sampling while the second sampling circuit operates at a lower speed for reference voltage sampling, thereby reducing overall kickback noise while maintaining high data sampling speed.
3Speed
If N-type transistors with minimized threshold voltage are used, then the operating voltage is reduced and speed is improved, but the circuit becomes more sensitive to substrate bias effects
Solution Approach 1:
The patent applies different transistor types strategically: N-type transistors are used in the second sampling circuit where low threshold voltage is critical for accurate reference voltage sampling, while P-type transistors are used in the first sampling circuit where substrate bias sensitivity would be more problematic. This local differentiation optimizes each circuit segment for its specific function.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present disclosure relates to the field of memory technologies and provides a data sampling circuit, comprising a first sampling module configured to respond to a signal from the data signal terminal and a signal from the reference signal terminal and to act on the first node and the second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on the third node and the fourth node; a latch module configured to input a high level to the first output terminal and input a low level to the second output terminal, or to input the low-level signal to the first output terminal and input the high-level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and an offset compensation module connected in parallel to the second sampling module and configured to compensate an offset voltage of the second sampling module. In this data sampling circuit, the second sampling module is additionally provided, and the offset compensation module is connected in parallel to the second sampling module, such that kickback noise is reduced.