Switched-Capacitor Sampling Circuit for Settling Error Cancellation
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Solution Overview
Problem
Existing sampling systems in digital signal processors suffer from settling errors due to incomplete charging/discharging of sampling capacitors, leading to voltage deviations and increased power consumption, with current methods like using strong voltage buffers or FIR/IIR filters being inefficient or costly in terms of power and noise.
Innovation Solution
A sampling system with switched-capacitor based settling error canceller circuits, utilizing additional sampling capacitors for charge redistribution to cancel settling errors, estimated through an online training process, and adjusted for process, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a voltage buffer with strong driving capability is used to reduce settling error, then the settling error is reduced, but the power consumption increases
Solution Approach 1:
The patent introduces an intermediary settling error canceller circuit that consists of additional sampling capacitors and switches. This canceller circuit mediates between the sampler circuit and the subsequent processing stages, canceling the settling error through charge redistribution without requiring a high-power voltage buffer.
Solution Approach 2:
The patent changes the operational parameters by using multiple phases (first phase for sampling, second phase for charge redistribution) and adjusting the capacitance values of the sampling capacitors in the canceller circuit to match the main sampling capacitors, thereby achieving error cancellation with low power consumption.
2Measurement precision
If a reset phase is provided to clear current memorized value before new sampling, then the settling error is reduced, but the sampling speed decreases due to the reset window
Solution Approach 1:
The patent employs periodic action by dividing the operation into alternating phases: during the first phase, the sampler circuit samples the input voltage; during the second phase, the settling error canceller circuit performs charge redistribution to cancel the error. This periodic switching allows error cancellation without interrupting the high-speed sampling flow.
3Measurement precision
If FIR or IIR filter is used to cancel settling error in DSP, then the settling error is reduced, but the noise and power consumption increase
Solution Approach 1:
The patent replaces the digital signal processing approach (FIR/IIR filters in DSP) with an analog circuit implementation. The settling error canceller circuit uses switched-capacitor charge redistribution in the analog domain to cancel errors, avoiding the noise and power overhead associated with digital filtering operations.
4Measurement precision
If additional sampling capacitors are used for settling error cancellation, then the settling error is reduced, but the device complexity increases
Solution Approach 1:
The additional sampling capacitors in the settling error canceller circuit serve multiple functions: they store the sampled voltage during the first phase, participate in charge redistribution during the second phase to cancel errors, and can be adjusted to match the capacitance values of the main sampling capacitors. This multi-functionality reduces the need for separate error cancellation hardware.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively cancels settling errors by charge redistribution, reducing power consumption and noise, while maintaining accuracy in high-speed sampling operations.
Implementation Method 1
comprises at least one sampling capacitor
Implementation Method 2
perform charge redistribution between the at least one sampling capacitor and the at least one second sampling capacitor
Data Source
AI summary
A sampling system includes a sampler circuit, a first settling error canceller circuit, and a second settling error canceller circuit. During a first phase, each of the sampler circuit and the first settling error canceller circuit perform a sampling operation, and the second settling error canceller circuit performs a holding operation. During a second phase, the sampler circuit and the second settling error canceller circuit perform charge redistribution, and the first settling error canceller circuit performs a holding operation. During a third phase, each of the sampler circuit and the second settling error canceller circuit performs a sampling operation, and the first settling error canceller circuit performs a holding operation. During a fourth phase, the sampler circuit and the first settling error canceller circuit perform charge redistribution, and the second settling error canceller circuit performs a holding operation.