Input Data Sampling Circuit Sleep Control for Lower Interface Power
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Solution Overview
Problem
The power consumption of data sampling units in semiconductor integrated circuits remains high due to the need to select a phase of clock appropriate for sampling from a synchronization pattern, especially during parallel sampling operations, which prevents these units from entering sleep mode effectively.
Innovation Solution
Incorporating a hysteresis circuit and a data sampling unit that detects sleep commands and selects an appropriate sampling clock phase, allowing the data sampling unit to be controlled into sleep mode, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the data sampling unit continuously operates to select appropriate clock phase for sampling payload data, then data sampling accuracy is maintained, but power consumption increases
Solution Approach 1:
The data sampling unit operates periodically based on frame structure. During interframe gaps longer than a frame period, the unit enters sleep mode to reduce power consumption. The line driver asserts a high level '1' during a bit period after the last bit of a frame to indicate transition to sleep mode, and exits sleep mode by driving a low level during at least an 8-bit period before the start of the initial bit in the synchronization sequence of a new frame.
2Use of energy by moving object
If the data sampling unit enters sleep mode to reduce power consumption, then energy efficiency improves, but the ability to sample data is lost
Solution Approach 1:
The line driver provides feedback signals to control the data sampling unit's operational state. A high level '1' asserted during a bit period immediately after the last bit of a frame indicates transition to sleep mode. To exit sleep mode, the line driver drives a low level during at least an 8-bit period before the start of the initial bit in the synchronization sequence of a new frame, ensuring the data sampling unit is ready to sample data when needed.
3Productivity
If parallel sampling operations are performed to increase data transfer speed, then productivity improves, but power consumption increases
Solution Approach 1:
The data sampling unit dynamically adjusts its operational mode based on data transfer requirements. During high-speed mode, parallel sampling operations are performed to increase data transfer speed. During interframe gaps longer than a frame period, the unit transitions to sleep mode to reduce power consumption, creating a dynamic balance between productivity and energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power consumption in sleep mode by controlling the data sampling unit into a low-power state, optimizing energy efficiency during high-speed data transfer operations.
Implementation Method 1
A hysteresis circuit has first and second input thresholds. The hysteresis circuit detects an input signal having a predetermined voltage range between the first and second input thresholds
Data Source
AI summary
The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.